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81. 发明申请

US20180285260A1 PERSISTENT CACHING OF MEMORY-SIDE CACHE CONTENT 审中-公开
公开(公告)号：US20180285260A1
公开(公告)日：2018-10-04
申请号：US15476866
申请日：2017-03-31
申请人： Intel Corporation
发明人： Patrick Lu , Karthik Kumar , Francesc Guim Bernat , Thomas Willhalm
IPC分类号： G06F12/06 , G06F12/0873 , G06F12/0868 , G06F12/0891 , G06F12/02 , G06F13/16 , G06F13/42
CPC分类号： G06F12/0638 , G06F12/0246 , G06F12/0868 , G06F12/0873 , G06F12/0891 , G06F13/1694 , G06F13/4239 , G06F2212/7201
摘要： Persistent caching of memory-side cache content for devices, systems, and methods are disclosed and discussed. In a system including both a volatile memory (VM) and a nonvolatile memory (NVM), both mapped to the system address space, software applications directly access the NVM, and a portion of the VM is used as a memory-side cache (MSC) for the NVM. When power is lost, at least a portion of the MSC cache contents is copied to a storage region in the NVM, which is restored to the MSC upon system reboot.

82. 发明申请

US20180284996A1 DYNAMICALLY COMPOSABLE COMPUTING SYSTEM, A DATA CENTER, AND METHOD FOR DYNAMICALLY COMPOSING A COMPUTING SYSTEM 审中-公开
公开(公告)号：US20180284996A1
公开(公告)日：2018-10-04
申请号：US15474044
申请日：2017-03-30
申请人： Intel Corporation
发明人： Francesc Guim Bernat , Mark Schmisseur , Karthik Kumar , Thomas Willhalm , Lidia Warnes
IPC分类号： G06F3/06
CPC分类号： G06F3/067 , G06F3/0605 , G06F3/0631 , G06F9/50
摘要： The present disclosure relates to a dynamically composable computing system. The dynamically composable computing system comprises at least one compute sled including a set of respective local computing hardware resources; a plurality of disaggregated memory modules; at least one disaggregated memory acceleration logic configured to perform one or more predefined computations on data stored in one or more of the plurality of disaggregated memory modules; and a resource manager module configured to assemble a composite computing node by associating, in accordance with requirements of a user, at least one of the plurality of disaggregated memory modules with the disaggregated memory acceleration logic to provide at least one accelerated disaggregated memory module and connecting the least one accelerated disaggregated memory module to the compute sled.

83. 发明申请

US20180267878A1 System, Apparatus And Method For Multi-Kernel Performance Monitoring In A Field Programmable Gate Array 审中-公开
公开(公告)号：US20180267878A1
公开(公告)日：2018-09-20
申请号：US15460385
申请日：2017-03-16
申请人： Intel Corporation
发明人： Francesc Guim Bernat , Karthik Kumar , Thomas Willhalm , Daniel Rivas Barragan , Patrick Lu
IPC分类号： G06F11/34 , G06F11/30 , H03K19/177
CPC分类号： G06F11/3409 , G06F11/3017 , H03K19/1776 , H03K19/17764
摘要： In one embodiment, a field programmable gate array (FPGA) includes: programmable logic to perform at least one function for a processor coupled to the FPGA; a performance monitor circuit including a set of performance monitors to be programmably associated with a first kernel to execute on the FPGA; and a monitor circuit to receive kernel registration information of the first kernel from the processor and program a first set of performance monitors for association with the first kernel based on the kernel registration information. Other embodiments are described and claimed.

84. 发明授权

US10038767B2 Technologies for fabric supported sequencers in distributed architectures 有权
公开(公告)号：US10038767B2
公开(公告)日：2018-07-31
申请号：US15260613
申请日：2016-09-09
申请人： Intel Corporation
发明人： Francesc Guim Bernat , Karthik Kumar , Thomas Willhalm , Raj K. Ramanujan , Daniel Rivas Barragan
IPC分类号： H04L12/50 , H04L29/08 , H04L1/16
CPC分类号： H04L69/324 , G06F15/173 , H04L1/1642 , H04L12/50 , H04L45/28 , H04L45/745 , H04L49/00
摘要： Technologies for using fabric supported sequencers in fabric architectures includes a network switch communicatively coupled to a plurality of computing nodes. The network switch is configured to receive an sequencer access message from one of the plurality of computing nodes that includes an identifier of a sequencing counter corresponding to a sequencer session and one or more operation parameters. The network switch is additionally configured to perform an operation on a value associated with the identifier of the sequencing counter as a function of the one or more operation parameters, increment the identifier of the sequencing counter, and associate a result of the operation with the incremented identifier of the sequencing counter. The network switch is further configured to transmit an acknowledgment of successful access to the computing node that includes the result of the operation and the incremented identifier of the sequencing counter. Other embodiments are described herein.

85. 发明申请

US20180150256A1 TECHNOLOGIES FOR DATA DEDUPLICATION IN DISAGGREGATED ARCHITECTURES 审中-公开
公开(公告)号：US20180150256A1
公开(公告)日：2018-05-31
申请号：US15716790
申请日：2017-09-27
申请人： Intel Corporation
发明人： Karthik Kumar , Francesc Guim Bernat , Thomas Willhalm , Mark A. Schmisseur
IPC分类号： G06F3/06
CPC分类号： G06F3/0641 , G06F3/0604 , G06F3/0608 , G06F3/0611 , G06F3/0613 , G06F3/0617 , G06F3/0647 , G06F3/065 , G06F3/0653 , G06F3/067 , G06F7/06 , G06F8/65 , G06F8/654 , G06F8/656 , G06F8/658 , G06F9/3851 , G06F9/3891 , G06F9/4401 , G06F9/4881 , G06F9/5038 , G06F9/505 , G06F9/544 , G06F11/0709 , G06F11/0751 , G06F11/079 , G06F11/1453 , G06F11/3006 , G06F11/3034 , G06F11/3055 , G06F11/3409 , G06F12/023 , G06F12/0284 , G06F12/0692 , G06F13/1652 , G06F15/80 , G06F16/1744 , G06F21/57 , G06F21/6218 , G06F21/73 , G06F21/76 , G06F2212/401 , G06F2212/402 , G06F2221/2107 , G06T1/20 , G06T1/60 , G06T9/005 , H01R13/4538 , H01R13/631 , H03K19/1731 , H03M7/3084 , H03M7/40 , H03M7/42 , H03M7/60 , H03M7/6011 , H03M7/6017 , H03M7/6029 , H04L9/0822 , H04L12/2881 , H04L12/4633 , H04L41/044 , H04L41/046 , H04L41/0816 , H04L41/0853 , H04L41/0896 , H04L41/12 , H04L41/142 , H04L43/04 , H04L43/06 , H04L43/08 , H04L43/0894 , H04L47/20 , H04L47/2441 , H04L47/78 , H04L49/104 , H04L61/2007 , H04L63/1425 , H04L67/10 , H04L67/1014 , H04L67/327 , H04L67/36 , H05K7/1452 , H05K7/1487
摘要： Technologies for providing data deduplication in a disaggregated architecture include a network device. The network device is to receive, from a compute sled, a request to write a data block to one or more data storage sleds and determine, for each of one or more data sub-blocks within the data block and from deduplication data indicative of physical addresses of data sub-blocks, whether each data sub-block is already stored in a data storage device of a data storage sled. Additionally, the network device is to write, in the deduplication data and in response to a determination that a data sub-block is already stored in a data storage device, a pointer to a physical address of the already-stored data sub-block in association with a logical address of the data sub-block.

86. 发明授权

US09535820B2 Technologies for application validation in persistent memory systems 有权
标题翻译：持久性存储器系统中的应用验证技术
公开(公告)号：US09535820B2
公开(公告)日：2017-01-03
申请号：US14670965
申请日：2015-03-27
申请人： Intel Corporation
发明人： Philip R. Lantz , Thomas Willhalm , Kirill Instrumentov , Karthik Kumar
IPC分类号： G06F9/44 , G06F11/36
CPC分类号： G06F11/3688 , G06F11/3648
摘要： Technologies for software testing include a computing device having persistent memory that includes a platform simulator and an application or other code module to be tested. The computing device generates a checkpoint for the application at a test location using the platform simulator. The computing device executes the application from the test location to an end location and traces all writes to persistent memory using the platform simulator. The computing device generates permutations of persistent memory writes that are allowed by the hardware specification of the computing device simulated by the platform simulator. The computing device replays each permutation from the checkpoint, simulates a power failure, and then invokes a user-defined test function using the platform simulator. The computing device may test different permutations of memory writes until the application's use of persistent memory is validated. Other embodiments are described and claimed.
摘要翻译：用于软件测试的技术包括具有持久存储器的计算设备，其包括平台模拟器和要测试的应用或其他代码模块。计算设备使用平台模拟器在测试位置生成应用程序的检查点。计算设备从测试位置执行应用程序到终端位置，并使用平台模拟器跟踪对持久存储器的所有写入。计算设备产生由平台模拟器模拟的计算设备的硬件规范允许的持久存储器写入的排列。计算设备从检查点重播每个置换，模拟电源故障，然后使用平台模拟器调用用户定义的测试功能。计算设备可以测试存储器写入的不同排列，直到应用程序使用永久存储器被验证为止。描述和要求保护其他实施例。

87. 发明申请

US20160342417A1 PROVIDING VECTOR SUB-BYTE DECOMPRESSION FUNCTIONALITY 审中-公开
标题翻译：提供矢量子字节分解功能
公开(公告)号：US20160342417A1
公开(公告)日：2016-11-24
申请号：US15225401
申请日：2016-08-01
申请人： INTEL CORPORATION
发明人： Tal Uliel , Elmoustapha Ould-Ahmed-Vall , Thomas Willhalm , Robert Valentine
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F9/30032 , G06F9/30109 , G06F9/30112 , G06F9/3889
摘要： Processing to execute SIMD vector sub-byte decompression functionality includes copying a first two bytes into the least significant portion of a first vector element, a second two bytes into the most significant portion, and copying a third two bytes into the least significant portion of a second vector element, and a fourth two bytes into the most significant portion. Processing continues by shifting the first vector element by a first shift count and the second vector element by a second shift count. Processing continues with copying the first two bytes and the third two bytes from the shifted first and second vector elements into a first destination vector element, and the second two bytes and the fourth two bytes from the shifted first and second vector elements into a second destination vector element, to at least partially restore an original sub-byte order of the sub-byte elements.
摘要翻译：执行SIMD向量子字节解压缩功能的处理包括将前两个字节复制到第一向量元素的最低有效部分，将第二个两个字节复制到最高有效部分，以及将第三个两个字节复制到第二矢量元素和第四个两个字节到最重要部分。通过将第一矢量元素移位第一移位计数和第二向量元素第二移位计数来继续处理。处理继续，将前两个字节和第三个两个字节从移位的第一和第二向量元素复制到第一目的地向量元素中，并且将第二个两个字节和第四个两个字节从被移位的第一和第二向量元素复制到第二目的地向量元素，以至少部分恢复子字节元素的原始子字节顺序。

88. 发明授权

US09442731B2 Packed two source inter-element shift merge processors, methods, systems, and instructions 有权
标题翻译：封装两个源间元素间移位合并处理器，方法，系统和指令
公开(公告)号：US09442731B2
公开(公告)日：2016-09-13
申请号：US14142738
申请日：2014-03-13
申请人： Intel Corporation
发明人： Tal Uliel , Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Mark J. Charney , Thomas Willhalm
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30018 , G06F9/30032 , G06F9/30036
摘要： A processor includes a decoder to receive an instruction that indicates first and second source packed data operands and at least one shift count. An execution unit is operable, in response to the instruction, to store a result packed data operand. Each result data element includes a first least significant bit (LSB) portion of a first data element of a corresponding pair of data elements in a most significant bit (MSB) portion, and a second MSB portion of a second data element of the corresponding pair in a LSB portion. One of the first LSB portion of the first data element and the second MSB portion of the second data element has a corresponding shift count number of bits. The other has a number of bits equal to a size of a data element of the first source packed data minus the corresponding shift count.
摘要翻译：处理器包括解码器，用于接收指示第一和第二源压缩数据操作数和至少一个移位计数的指令。执行单元响应于该指令可操作地存储结果打包数据操作数。每个结果数据元素包括最高有效位（MSB）部分中对应的一对数据元素的第一数据元素的第一最低有效位（LSB）部分和相应对的第二数据元素的第二MSB部分在LSB部分。第一数据元素的第一LSB部分和第二数据元素的第二MSB部分之一具有相应的移位计数位数。另一个具有等于第一源打包数据的数据元素减去相应移位计数的大小的位数。

89. 发明授权

US12088507B2 Scalable edge computing 有权
公开(公告)号：US12088507B2
公开(公告)日：2024-09-10
申请号：US17861949
申请日：2022-07-11
申请人： Intel Corporation
发明人： Francesc Guim Bernat , Karthik Kumar , Thomas Willhalm , Mark A. Schmisseur , Timothy Verrall
IPC分类号： G06F15/173 , G06F9/50 , G06N20/00 , H04L47/70 , H04L47/765 , H04L47/83
CPC分类号： H04L47/765 , G06F9/5011 , G06N20/00 , H04L47/824 , H04L47/83
摘要： There is disclosed in one example an application-specific integrated circuit (ASIC), including: an artificial intelligence (AI) circuit; and circuitry to: identify a flow, the flow including traffic diverted from a core cloud service of a network to be serviced by an edge node closer to an edge of the network than to the core of the network; receive telemetry related to the flow, the telemetry including fine-grained and flow-level network monitoring data for the flow; operate the AI circuit to predict, from the telemetry, a future service-level demand for the edge node; and cause a service parameter of the edge node to be tuned according to the prediction.

90. 发明授权

US12058036B2 Technologies for quality of service based throttling in fabric architectures 有权
公开(公告)号：US12058036B2
公开(公告)日：2024-08-06
申请号：US17746677
申请日：2022-05-17
申请人： Intel Corporation
发明人： Francesc Guim Bernat , Karthik Kumar , Thomas Willhalm , Raj Ramanujan , Brian Slechta
IPC分类号： H04L45/302 , H04L47/125 , H04L47/26 , H04L49/10 , H04L49/20
CPC分类号： H04L45/302 , H04L47/125 , H04L47/26 , H04L49/10 , H04L49/205
摘要： Technologies for quality of service based throttling in a fabric architecture include a network node of a plurality of network nodes interconnected across the fabric architecture via an interconnect fabric. The network node includes a host fabric interface (HFI) configured to facilitate the transmission of data to/from the network node, monitor quality of service levels of resources of the network node used to process and transmit the data, and detect a throttling condition based on a result of the monitored quality of service levels. The HFI is further configured to generate and transmit a throttling message to one or more of the interconnected network nodes in response to having detected a throttling condition. The HFI is additionally configured to receive a throttling message from another of the network nodes and perform a throttling action on one or more of the resources based on the received throttling message. Other embodiments are described herein.

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