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81. 发明授权

US08018776B2 Verification method for nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件的验证方法
公开(公告)号：US08018776B2
公开(公告)日：2011-09-13
申请号：US12836243
申请日：2010-07-14
申请人： Hiroyuki Miyake , Mitsuaki Osame , Aya Miyazaki
发明人： Hiroyuki Miyake , Mitsuaki Osame , Aya Miyazaki
IPC分类号： G11C11/34
CPC分类号： G11C16/3436 , G11C16/26
摘要： The present invention provides nonvolatile semiconductor memory devices which operate with low power consumption. In a nonvolatile semiconductor memory device, a plurality of nonvolatile memory elements are connected in series. The plurality of nonvolatile memory elements include a semiconductor layer including a channel forming region and a control gate provided to overlap with the channel forming region. Operations of write, erase, a first read, and a second read in a verify operation of data to the nonvolatile memory elements, are conducted by changing voltage to the control gates of the nonvolatile memory elements. The second read in the verify operation after erase operation is conducted by changing only one of a potential of the control gate of a nonvolatile memory element which are selected from the plurality of nonvolatile memory elements, and as the potential, a potential different from a potential of the first read is used.
摘要翻译：本发明提供了以低功耗工作的非易失性半导体存储器件。在非易失性半导体存储器件中，多个非易失性存储元件串联连接。多个非易失性存储元件包括包括沟道形成区域的半导体层和设置成与沟道形成区域重叠的控制栅极。通过将电压改变为非易失性存储器元件的控制栅极来进行对非易失性存储器元件的数据的验证操作的写入，擦除，第一读取和第二次读取操作。在擦除操作之后的验证操作中的第二次读取是通过仅改变从多个非易失性存储元件中选择的非易失性存储元件的控制栅极的电位中的一个，并且作为电势，与电位不同的电位的第一次读取被使用。

82. 发明授权

US07961525B2 Method for deleting data from NAND type nonvolatile memory 有权
标题翻译：从NAND型非易失性存储器中删除数据的方法
公开(公告)号：US07961525B2
公开(公告)日：2011-06-14
申请号：US12491395
申请日：2009-06-25
申请人： Mitsuaki Osame , Hiroyuki Miyake , Aya Miyazaki , Shunpei Yamazaki
发明人： Mitsuaki Osame , Hiroyuki Miyake , Aya Miyazaki , Shunpei Yamazaki
IPC分类号： G11C16/04
CPC分类号： G11C16/14 , G11C8/10 , G11C16/0483 , G11C16/08 , H01L21/28273 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11529 , H01L27/11546
摘要： To provide a method of releasing charges which have been injected into charge accumulating layers of nonvolatile memory elements without using a substrate terminal such as a p well or an n well, as a method for deleting data from a NAND-type nonvolatile memory. In the method for deleting data from the NAND-type nonvolatile memory, charges stored in a charge accumulating layer of a first nonvolatile memory element are released by applying a first potential to a bit line and a source line, a second potential to a control gate of the first nonvolatile memory element, and a third potential which is different from the second potential to a control gate of a second nonvolatile memory element.
摘要翻译：作为从NAND型非易失性存储器中删除数据的方法，提供一种释放已经注入到非易失性存储元件的电荷累积层中而不使用诸如p阱或n阱的衬底端子的电荷的方法。在从NAND型非易失性存储器中删除数据的方法中，通过将第一电位施加到位线和源极线，将第二电位施加到控制栅极来释放存储在第一非易失性存储元件的电荷累积层中的电荷以及与第二电位不同的第三电位连接到第二非易失性存储元件的控制栅极。

83. 发明申请

US20110089927A1 VOLTAGE REGULATOR CIRCUIT 有权
标题翻译：电压调节器电路
公开(公告)号：US20110089927A1
公开(公告)日：2011-04-21
申请号：US12909556
申请日：2010-10-21
申请人： Shunpei Yamazaki , Hiroyuki Miyake , Masashi Tsubuku , Kosei Noda
发明人： Shunpei Yamazaki , Hiroyuki Miyake , Masashi Tsubuku , Kosei Noda
IPC分类号： G05F3/08
CPC分类号： H01L29/78696 , H01L21/84 , H01L27/105 , H01L27/1225 , H01L27/124 , H01L27/1255 , H01L29/24 , H01L29/66969 , H01L29/7869 , H02M3/073 , H02M3/158
摘要： A transistor includes a gate, a source, and a drain, the gate is electrically connected to the source or the drain, a first signal is input to one of the source and the drain, and an oxide semiconductor layer whose carrier concentration is 5×1014/cm3 or less is used for a channel formation layer. A capacitor includes a first electrode and a second electrode, the first electrode is electrically connected to the other of the source and the drain of the transistor, and a second signal which is a clock signal is input to the second electrode. A voltage of the first signal is stepped up or down to obtain a third signal which is output as an output signal through the other of the source and the drain of the transistor.
摘要翻译：晶体管包括栅极，源极和漏极，栅极电连接到源极或漏极，第一信号被输入到源极和漏极中的一个，以及载流子浓度为5× 1014 / cm3以下用于沟道形成层。电容器包括第一电极和第二电极，第一电极电连接到晶体管的源极和漏极中的另一个，并且作为时钟信号的第二信号被输入到第二电极。第一信号的电压被升高或降低以获得通过晶体管的源极和漏极中的另一个输出作为输出信号的第三信号。

84. 发明授权

US07911500B2 Image processing device, computer readable recording medium, and image processing method 有权
标题翻译：图像处理装置，计算机可读记录介质和图像处理方法
公开(公告)号：US07911500B2
公开(公告)日：2011-03-22
申请号：US11962596
申请日：2007-12-21
申请人： Shingo Uchihashi , Hiroyuki Miyake
发明人： Shingo Uchihashi , Hiroyuki Miyake
IPC分类号： H04N5/225 , H04N9/04 , H04N17/00 , H04N17/02
CPC分类号： H04N17/00 , H04N9/3194
摘要： An image processing device includes: a connecting unit that connects a projecting device and an image capture device, at least one of the projecting device and the image capture device having an adjustable position; an acquiring unit that acquires an image captured by the image capture device capturing an image of a reference pattern that is projected by the projecting device and indicates an effective projecting range of the projecting device; a color converting unit that extracts the reference pattern from the captured image, and performs a color conversion on the extracted reference pattern; an enlarging/reducing unit that enlarges or reduces the color-converted reference pattern in accordance with the ratio between the maximum effective imaging range of the image capture device and the effective projecting range of the projecting device; a superimposing unit that superimposes the enlarged or reduced reference pattern on a reference pattern yet to be projected; and an output unit that outputs the reference pattern superimposed by the superimposing unit to the projecting device.
摘要翻译：图像处理装置包括：连接投影装置和图像捕获装置的连接单元，所述投影装置和所述图像捕获装置中的至少一个具有可调节位置; 获取单元，其获取由所述图像拍摄装置捕获的图像，所述图像捕获装置捕获由所述投影装置投影的参考图案的图像，并且指示所述投影装置的有效投影范围; 色彩转换单元，从拍摄图像中提取参考图案，并对所提取的参考图案进行颜色转换; 放大/缩小单元，其根据图像捕获装置的最大有效成像范围与投影装置的有效投影范围之间的比率放大或缩小变色参考图案; 叠加单元，其将放大或缩小的参考图案叠加在待投影的参考图案上; 以及输出单元，其将由叠加单元叠加的参考图案输出到投影装置。

85. 发明授权

US07781768B2 Display device, method for manufacturing the same, and electronic device having the same 有权
标题翻译：显示装置及其制造方法以及具有该显示装置的电子装置
公开(公告)号：US07781768B2
公开(公告)日：2010-08-24
申请号：US11819154
申请日：2007-06-25
申请人： Masayuki Sakakura , Hiroyuki Miyake
发明人： Masayuki Sakakura , Hiroyuki Miyake
IPC分类号： H01L33/00
CPC分类号： H01L27/1288 , H01L27/1214 , H01L27/1274 , H01L27/3244
摘要： In a case where a p-channel thin film transistor is used as a thin film transistor that is electrically connected to a light-emitting element and drives the light-emitting element, a value of cutoff current of the p-channel thin film transistor is made lower than that of a p-channel thin film transistor of a driver circuit. Specifically, channel doping is selectively performed on a semiconductor layer of a thin film transistor included in a pixel.
摘要翻译：在使用p沟道薄膜晶体管作为电连接到发光元件并驱动发光元件的薄膜晶体管的情况下，p沟道薄膜晶体管的截止电流值为比驱动电路的p沟道薄膜晶体管低。具体地，在包括在像素中的薄膜晶体管的半导体层上选择性地进行沟道掺杂。

86. 发明授权

US07692973B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07692973B2
公开(公告)日：2010-04-06
申请号：US11727209
申请日：2007-03-23
申请人： Aya Miyazaki , Mitsuaki Osame , Hiroyuki Miyake , Shunpei Yamazaki
发明人： Aya Miyazaki , Mitsuaki Osame , Hiroyuki Miyake , Shunpei Yamazaki
IPC分类号： G11C11/03
CPC分类号： H01L29/7881 , H01L21/84 , H01L27/105 , H01L27/11526 , H01L27/11529 , H01L27/12 , H01L29/42324
摘要： A semiconductor device is provided, which comprises at least a cell including a plurality of memory elements connected in series. Each of the plurality of memory elements includes a channel formation region, source and drain regions, a floating gate, and a control gate. Each of the source and drain regions is electrically connected to an erasing line through a semiconductor impurity region.
摘要翻译：提供一种半导体器件，其包括至少一个包括串联连接的多个存储元件的单元。多个存储元件中的每一个包括沟道形成区域，源极和漏极区域，浮动栅极和控制栅极。源区和漏区中的每一个通过半导体杂质区电连接到擦除线。

87. 发明授权

US07663578B2 Semiconductor device, display device and electronic device 有权
标题翻译：半导体器件，显示器件和电子器件
公开(公告)号：US07663578B2
公开(公告)日：2010-02-16
申请号：US11620345
申请日：2007-01-05
申请人： Hiroyuki Miyake
发明人： Hiroyuki Miyake
IPC分类号： G09G5/00
CPC分类号： G09G3/3258 , G09G2300/0857 , G09G2310/0251 , G09G2310/0262 , G09G2320/029 , G09G2320/041 , G09G2320/043
摘要： A potential which is applied to a gate electrode of a driving transistor in accordance with an emission state or a non-emission state of a light-emitting element fluctuates due to noise or leakage from a selection transistor, or the like, which causes a problem in that the driving transistor cannot turn on or off normally and malfunctions. The present invention includes a transistor connected to a light-emitting element, a power source line, a scan line, a memory circuit, and a switching circuit, in which the transistor controls light emission or non light emission of the light-emitting element, and the switching circuit controlled by the scan line conducts switching between the transistor, and the memory circuit and the power source line, and applies an input potential to the transistor.
摘要翻译：根据发光元件的发光状态或非发光状态施加到驱动晶体管的栅电极的电位由于选择晶体管等的噪声或泄漏而波动，这导致问题因为驱动晶体管不能正常导通或断开，故障。本发明包括连接到发光元件的晶体管，电源线，扫描线，存储器电路和开关电路，其中晶体管控制发光元件的发光或非发光，并且由扫描线控制的开关电路导通晶体管与存储器电路与电源线之间的切换，并向晶体管施加输入电位。

88. 发明授权

US07656380B2 Display device 有权
标题翻译：显示设备
公开(公告)号：US07656380B2
公开(公告)日：2010-02-02
申请号：US09970929
申请日：2001-10-05
申请人： Jun Koyama , Tomoaki Atsumi , Hiroyuki Miyake
发明人： Jun Koyama , Tomoaki Atsumi , Hiroyuki Miyake
IPC分类号： G09G3/36 , G11C19/00
CPC分类号： G09G3/3688 , G09G3/3677 , G09G5/02 , G09G2310/0283 , G09G2310/0289 , G09G2330/021 , H01L27/12 , H01L27/1214
摘要： This invention provides a driving circuit for a display device, for accomplishing low power consumption by use of a level shifter capable of reliably converting signals having low voltage amplitude. A source signal line driving circuit is divided into a plurality of units. Pulses outputted from a shift register, etc, are used to execute ON/OFF control of the operation of a current supply source to the level shifter of each divided unit. The supply of the current to the level shifter is suspended in the stage not containing the circuit that outputs the pulses, but is made to only the unit including the shift register of the operating stage. In consequence, low power consumption can be achieved.
摘要翻译：本发明提供一种用于显示装置的驱动电路，用于通过使用能够可靠地转换具有低电压幅度的信号的电平转换器来实现低功耗。源极信号线驱动电路被分成多个单元。从移位寄存器等输出的脉冲用于对每个分割单元的电平移位器执行电流源的操作的ON / OFF控制。向电平移位器的电流的供给被暂停在不包含输出脉冲的电路的级中，但是仅被构成包括操作级的移位寄存器的单元。因此，可以实现低功耗。

89. 发明申请

US20090257283A1 METHOD FOR DELETING DATA FROM NAND TYPE NONVOLATILE MEMORY 有权
标题翻译：从NAND型非易失性存储器中删除数据的方法
公开(公告)号：US20090257283A1
公开(公告)日：2009-10-15
申请号：US12491395
申请日：2009-06-25
申请人： Mitsuaki Osame , Hiroyuki Miyake , Aya Miyazaki , Shunpei Yamazaki
发明人： Mitsuaki Osame , Hiroyuki Miyake , Aya Miyazaki , Shunpei Yamazaki
IPC分类号： G11C16/04 , H01L29/792
CPC分类号： G11C16/14 , G11C8/10 , G11C16/0483 , G11C16/08 , H01L21/28273 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11529 , H01L27/11546
摘要： To provide a method of releasing charges which have been injected into charge accumulating layers of nonvolatile memory elements without using a substrate terminal such as a p well or an n well, as a method for deleting data from a NAND-type nonvolatile memory. In the method for deleting data from the NAND-type nonvolatile memory, charges stored in a charge accumulating layer of a first nonvolatile memory element are released by applying a first potential to a bit line and a source line, a second potential to a control gate of the first nonvolatile memory element, and a third potential which is different from the second potential to a control gate of a second nonvolatile memory element.
摘要翻译：作为从NAND型非易失性存储器中删除数据的方法，提供一种释放已经注入到非易失性存储元件的电荷累积层中而不使用诸如p阱或n阱的衬底端子的电荷的方法。在从NAND型非易失性存储器中删除数据的方法中，通过将第一电位施加到位线和源极线，将第二电位施加到控制栅极来释放存储在第一非易失性存储元件的电荷累积层中的电荷以及与第二电位不同的第三电位连接到第二非易失性存储元件的控制栅极。

90. 发明申请

US20070230254A1 Method for deleting data from NAND type nonvolatile memory 有权
标题翻译：从NAND型非易失性存储器中删除数据的方法
公开(公告)号：US20070230254A1
公开(公告)日：2007-10-04
申请号：US11716672
申请日：2007-03-12
申请人： Mitsuaki Osame , Hiroyuki Miyake , Aya Miyazaki , Shunpei Yamazaki
发明人： Mitsuaki Osame , Hiroyuki Miyake , Aya Miyazaki , Shunpei Yamazaki
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/14 , G11C8/10 , G11C16/0483 , G11C16/08 , H01L21/28273 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11529 , H01L27/11546
摘要： To provide a method of releasing charges which have been injected into charge accumulating layers of nonvolatile memory elements without using a substrate terminal such as a p well or an n well, as a method for deleting data from a NAND-type nonvolatile memory. In the method for deleting data from the NAND-type nonvolatile memory, charges stored in a charge accumulating layer of a first nonvolatile memory element are released by applying a first potential to a bit line and a source line, a second potential to a control gate of the first nonvolatile memory element, and a third potential which is different from the second potential to a control gate of a second nonvolatile memory element.
摘要翻译：作为从NAND型非易失性存储器中删除数据的方法，提供一种释放已经注入到非易失性存储元件的电荷累积层中而不使用诸如p阱或n阱的衬底端子的电荷的方法。在从NAND型非易失性存储器中删除数据的方法中，通过将第一电位施加到位线和源极线，将第二电位施加到控制栅极来释放存储在第一非易失性存储元件的电荷累积层中的电荷以及与第二电位不同的第三电位连接到第二非易失性存储元件的控制栅极。

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