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81. 发明申请

US20090190399A1 SEMICONDUCTOR MEMORY DEVICE CAPABLE OF CORRECTING A READ LEVEL PROPERLY 有权
标题翻译：可修正读取电平的半导体存储器件
公开(公告)号：US20090190399A1
公开(公告)日：2009-07-30
申请号：US12416750
申请日：2009-04-01
申请人： Noboru Shibata , Hiroshi Sukegawa
发明人： Noboru Shibata , Hiroshi Sukegawa
IPC分类号： G11C16/02 , G11C16/06
CPC分类号： G11C16/0483 , G11C11/5642 , G11C16/12 , G11C16/26 , G11C16/3418 , G11C2211/5646 , G11C2211/565
摘要： In a memory cell array, a plurality of memory cells each of which stores a plurality of bits are connected to a plurality of word lines and a plurality of bit lines and are arranged in a matrix. Control portions read a threshold level of a second memory cell adjacent to a first memory cell in the memory cell array, determine a correction level according to the threshold level read from the second memory cell, add the determined correction level to a read level of the first memory cell, and then read the threshold level of the first memory cell. A storage portion stores the correction level.
摘要翻译：在存储单元阵列中，存储多个位的多个存储单元被连接到多个字线和多个位线并且以矩阵形式排列。控制部分读取与存储单元阵列中的第一存储器单元相邻的第二存储单元的阈值电平，根据从第二存储器单元读取的阈值电平确定校正电平，将所确定的校正电平加到读出电平第一存储器单元，然后读取第一存储器单元的阈值电平。存储部存储校正等级。

82. 发明授权

US07525839B2 Semiconductor memory device capable of correcting a read level properly 有权
标题翻译：能够正确地校正读取电平的半导体存储器件
公开(公告)号：US07525839B2
公开(公告)日：2009-04-28
申请号：US11753143
申请日：2007-05-24
申请人： Noboru Shibata , Hiroshi Sukegawa
发明人： Noboru Shibata , Hiroshi Sukegawa
IPC分类号： G11C7/10
CPC分类号： G11C16/0483 , G11C11/5642 , G11C16/12 , G11C16/26 , G11C16/3418 , G11C2211/5646 , G11C2211/565
摘要： In a memory cell array, a plurality of memory cells each of which stores a plurality of bits are connected to a plurality of word lines and a plurality of bit lines and are arranged in a matrix. Control portions read a threshold level of a second memory cell adjacent to a first memory cell in the memory cell array, determine a correction level according to the threshold level read from the second memory cell, add the determined correction level to a read level of the first memory cell, and then read the threshold level of the first memory cell. A storage portion stores the correction level.
摘要翻译：在存储单元阵列中，存储多个位的多个存储单元被连接到多个字线和多个位线并且以矩阵形式排列。控制部分读取与存储单元阵列中的第一存储器单元相邻的第二存储单元的阈值电平，根据从第二存储器单元读取的阈值电平确定校正电平，将所确定的校正电平加到读出电平第一存储器单元，然后读取第一存储器单元的阈值电平。存储部存储校正等级。

83. 发明授权

US07483304B2 Semiconductor memory device capable of setting a negative threshold voltage 有权
标题翻译：能够设定负阈值电压的半导体存储器件
公开(公告)号：US07483304B2
公开(公告)日：2009-01-27
申请号：US12055074
申请日：2008-03-25
申请人： Noboru Shibata
发明人： Noboru Shibata
IPC分类号： G11C16/04
CPC分类号： G11C16/12 , G11C11/5628 , G11C16/0483 , G11C16/30 , G11C16/3454
摘要： In a memory cell array, a plurality of memory cells connected to word lines and bit lines are arranged in a matrix. A control circuit controls the potentials of the word lines and bit lines. The control circuit, when reading data from the memory cell connected to a first one of the bit lines, supplies a first voltage to a second bit line provided next to the first bit line and to a source line of the memory cell array.
摘要翻译：在存储单元阵列中，连接到字线和位线的多个存储单元被布置成矩阵。控制电路控制字线和位线的电位。控制电路当从连接到第一位线的存储单元读取数据时，将第一电压提供给位于第一位线旁边的第二位线和存储单元阵列的源极线。

84. 发明授权

US07443734B2 Semiconductor memory device with a voltage generating circuit which generates a plurality of voltages using a small number of items of data 有权
标题翻译：具有电压产生电路的半导体存储器件，其使用少量数据产生多个电压
公开(公告)号：US07443734B2
公开(公告)日：2008-10-28
申请号：US11531920
申请日：2006-09-14
申请人： Noboru Shibata
发明人： Noboru Shibata
IPC分类号： G11C11/34
CPC分类号： G11C16/12 , G11C8/08 , G11C16/0483 , G11C16/3459
摘要： In a memory cell array, a plurality of memory cells connected to word lines and bit lines are arranged in a matrix. A storage section stores an initial value of a write voltage corresponding to a first write operation and a correction value for correcting the write voltage. A voltage generating circuit generates a word line write voltage in a first write operation or a second write operation on the basis of the initial value and correction value of the write voltage stored in the storage section.
摘要翻译：在存储单元阵列中，连接到字线和位线的多个存储单元被布置成矩阵。存储部存储对应于第一写入操作的写入电压的初始值和用于校正写入电压的校正值。电压产生电路基于存储在存储部中的写入电压的初始值和校正值，在第一写入操作或第二写入操作中产生字线写入电压。

85. 发明授权

US07394695B2 Nonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cells 有权
标题翻译：具有连接到存储单元的位线的多个数据存储部分的非易失性半导体存储器
公开(公告)号：US07394695B2
公开(公告)日：2008-07-01
申请号：US11511488
申请日：2006-08-29
申请人： Ken Takeuchi , Tomoharu Tanaka , Noboru Shibata
发明人： Ken Takeuchi , Tomoharu Tanaka , Noboru Shibata
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C7/1051 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/12 , G11C16/24 , G11C16/3431 , G11C16/3445 , G11C16/3459 , G11C2211/5621 , G11C2211/5642 , G11C2211/5643 , G11C2211/5649 , G11C2211/565 , G11C2216/14
摘要： Data having three values or more is stored in a memory cell in a nonvolatile manner. A data circuit has a plurality of storage circuits. One of the plurality of storage circuits is a latch circuit. Another one of the plurality of storage circuits is a capacitor. The latch circuit and the capacitor function to temporarily store program/read data having two bits or more. Data held by the capacitor is refreshed using the latch circuit if data variation due to leakage causes a program. As a result, the data circuit does not become large in size even if multi-level data is used.
摘要翻译：具有三个以上值的数据以非易失性方式存储在存储单元中。数据电路具有多个存储电路。多个存储电路中的一个是锁存电路。多个存储电路中的另一个是电容器。锁存电路和电容器用于临时存储具有两位或更多位的程序/读数据。如果由于泄漏引起的数据变化导致程序，则使用锁存电路来刷新由电容器保持的数据。结果，即使使用多级数据，数据电路也不会变大。

86. 发明授权

US07394691B2 Semiconductor memory device which prevents destruction of data 有权
标题翻译：防止数据破坏的半导体存储器件
公开(公告)号：US07394691B2
公开(公告)日：2008-07-01
申请号：US11498142
申请日：2006-08-03
申请人： Noboru Shibata , Hiroshi Sukegawa
发明人： Noboru Shibata , Hiroshi Sukegawa
IPC分类号： G11C11/34 , G11C7/00 , G11C29/00
CPC分类号： G11C11/5642 , G11C11/5628 , G11C16/0483
摘要： A plurality of memory cells each storing n values (n is a natural number which is not smaller than 3) are arranged in a matrix form in a memory cell array, and each memory cell is connected with a word line and a bit line. Each memory cell stores the n-valued data by a first write operation and a second write operation. A read section sets a potential of a word line, and reads data from a memory cell in the memory cell array. If data read by the read section and written in the second write operation includes an uncorrectable error, a control section changes a potential of a word line supplied to the read section when reading data written in the first write operation.
摘要翻译：每个存储n个值的多个存储单元（n是不小于3的自然数）以矩阵形式布置在存储单元阵列中，并且每个存储单元与字线和位线连接。每个存储单元通过第一写操作和第二写操作来存储n值数据。读取部分设置字线的电位，并从存储器单元阵列中的存储单元读取数据。如果由读取部分读取并写入第二写入操作的数据包括不可校正的错误，则当读取在第一写入操作中写入的数据时，控制部分改变提供给读取部分的字线的电位。

87. 发明授权

US07295468B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07295468B2
公开(公告)日：2007-11-13
申请号：US11401016
申请日：2006-04-05
申请人： Noboru Shibata
发明人： Noboru Shibata
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C11/5621 , G11C16/0483 , G11C16/3454 , G11C2211/5621 , G11C2211/5642
摘要： A page mode multi-level NAND-type memory employs two different verify levels per data state and comprises a first data storage circuit which is connected to a memory cell and which stores externally inputted data of a first logic level or a second logic level, a second data storage circuit which is connected to the memory cell and which stores the data of the first logic level or second logic level read from the memory cell, and a control circuit which controls the memory cell and the first and second data storage circuits and which reproduces the externally inputted data and writing the data into the memory cell.
摘要翻译：页面模式多级NAND型存储器对每个数据状态采用两个不同的验证电平，并且包括连接到存储器单元并且存储外部输入的第一逻辑电平或第二逻辑电平的数据的第一数据存储电路，第二数据存储电路，连接到存储单元，并存储从存储单元读取的第一逻辑电平或第二逻辑电平的数据;以及控制电路，其控制存储单元以及第一和第二数据存储电路，再现外部输入的数据并将数据写入存储单元。

88. 发明申请

US20070133291A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20070133291A1
公开(公告)日：2007-06-14
申请号：US11610193
申请日：2006-12-13
申请人： Yasuyuki FUKUDA , Noboru Shibata
发明人： Yasuyuki FUKUDA , Noboru Shibata
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/04 , G11C29/82
摘要： A nonvolatile semiconductor memory device of the present invention is characterized in that, when data is written to a flag cell area, every other flag cell in the direction of one bit line BL among a plurality of flag cells 15 connected to the bit line BL is written with data and every other flag cell in the direction of one word line WL among a plurality of flag cells 15 connected to the word line WL is written with data. The arrangement as described above prevents a flag cell 15 from being influenced by the capacitive coupling of a neighboring flag cell 15 adjacent to the flag cell 15 in the direction of the word line WL. Thus, data (flag data) memorized by the flag cell 15 can have improved reliability.
摘要翻译：本发明的非易失性半导体存储器件的特征在于，当数据被写入标志单元区域时，连接到位线BL的多个标志单元15中的一个位线BL的方向上的每隔一个标志单元是在与字线WL连接的多个标志单元15中的一个字线WL的方向上用数据和每隔一个的标志单元写入数据。如上所述的布置防止了标志单元15受到在字线WL的方向上与标志单元15相邻的相邻标记单元15的电容耦合的影响。因此，由标志单元15存储的数据（标志数据）可以提高可靠性。

89. 发明申请

US20070109854A1 SEMICONDUCTOR MEMORY DEVICE CAPABLE OF MEMORIZING MULTIVALUED DATA 有权
标题翻译：可存储多个数据的半导体存储器件
公开(公告)号：US20070109854A1
公开(公告)日：2007-05-17
申请号：US11556388
申请日：2006-11-03
申请人： Noboru Shibata
发明人： Noboru Shibata
IPC分类号： G11C14/00
CPC分类号： G11C16/3418 , G11C11/5628 , G11C16/0483 , G11C16/3427 , G11C2211/5621 , G11C2211/5642 , G11C2211/565
摘要： In a memory cell array, a plurality of memory cells connected to word lines and bit lines are arranged in a matrix. A data storage circuit is connected to the bit lines and stores write data. The data storage circuit includes at least one static latch circuit and a plurality of dynamic latch circuits when setting 2k threshold voltages (k is a natural number equal to 3 or more) in each memory cell in the memory cell array. A control circuit refreshes data by moving the data in one of the plurality of dynamic latch circuits to the static latch circuit and further moving the data in the static latch circuit to one of the plurality of dynamic latch circuits.
摘要翻译：在存储单元阵列中，连接到字线和位线的多个存储单元被布置成矩阵。数据存储电路连接到位线并存储写入数据。数据存储电路在存储器中的每个存储器单元中设置2个阈值电压（k为等于3或更大的自然数）时，至少包括一个静态锁存电路和多个动态锁存电路单元格阵列。控制电路通过将多个动态锁存电路之一中的数据移动到静态锁存电路来刷新数据，并且将静态锁存电路中的数据进一步移动到多个动态锁存电路之一。

90. 发明授权

US07164605B2 Semiconductor memory device and electric device with the same 有权
标题翻译：半导体存储器件和电器件相同
公开(公告)号：US07164605B2
公开(公告)日：2007-01-16
申请号：US11305193
申请日：2005-12-19
申请人： Koichi Kawai , Tomoharu Tanaka , Noboru Shibata
发明人： Koichi Kawai , Tomoharu Tanaka , Noboru Shibata
IPC分类号： G11C16/06
CPC分类号： G11C16/3468
摘要： A semiconductor memory device includes: a plurality of cell array blocks in each of which a plurality of memory cells are arranged; address decode circuits for selecting memory cells in the cell array blocks; sense amplifier circuits for reading cell data of the cell array blocks; and a busy signal generation circuit for generating a busy signal to the chip external, wherein in a first read cycle selecting a first area in a first cell array block, cell data read operations for the first area of the first cell array block and a second area of a second cell array block are simultaneously executed, while the busy signal generation circuit generates a true busy signal, and then a read data output operation is executed for outputting the read out data of the first area held in the sense amplifier circuits to the chip external, and in a second read cycle selecting the second area in the second cell array block, after the busy signal generation circuit has output a dummy busy signal shorter in time length than the true busy signal without executing cell data read operation, a read data output operation is executed for outputting the read out data of the second area held in the sense amplifier circuits to the chip external.
摘要翻译：半导体存储器件包括：多个单元阵列块，每个单元阵列块中布置有多个存储单元; 用于选择单元阵列块中的存储单元的地址解码电路; 用于读取单元阵列块的单元数据的读出放大器电路; 以及用于向芯片外部产生忙信号的忙信号产生电路，其中在第一读周期中选择第一单元阵列块中的第一区，对第一单元阵列块的第一区进行单元数据读操作，同时执行第二单元阵列块的区域，而忙信号产生电路产生真正的忙信号，然后执行读数据输出操作，以将保持在读出放大器电路中的第一区域的读出数据输出到芯片外部，并且在第二读取周期中选择第二单元阵列块中的第二区域，在忙信号产生电路在不执行单元数据读取操作的情况下输出比真实忙信号更短的时间长度的虚拟忙信号，读取执行数据输出操作，以将保持在读出放大器电路中的第二区域的读出数据输出到芯片外部。

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