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81. 发明授权

US08104026B2 Compiler register allocation and compilation 失效
标题翻译：编译器寄存器分配和编译
公开(公告)号：US08104026B2
公开(公告)日：2012-01-24
申请号：US11927355
申请日：2007-10-29
申请人： Akira Koseki , Hideaki Komatsu
发明人： Akira Koseki , Hideaki Komatsu
IPC分类号： G06F9/44
CPC分类号： G06F8/441
摘要： Assigns suitable registers to a plurality of variables. A compiler converts a source program into instructions for a processor having: a simultaneously used variable acquisition section which obtains, with respect to each of a plurality of variables used in the source program, some of the other variables used simultaneously with the variable; an allocation sequence generation section which generates a plurality of allocation sequences between the plurality of variables to allocate each variable to one of the plurality of registers different from those to which some of the other variables used simultaneously with the variable are allocated; an allocation priority acquisition section which obtains allocation priorities indicating to which one of the plurality of registers each variable is allocated with priority; and a register allocation section which allocates the variables to registers in accordance with an allocation sequence selected on the basis of the allocation priorities.
摘要翻译：将适当的寄存器分配给多个变量。编译器将源程序转换为具有以下处理器的指令：具有：同时使用的变量获取部分，其针对源程序中使用的多个变量中的每一个获得与该变量同时使用的一些其它变量; 分配序列生成部，其生成所述多个变量之间的多个分配序列，以将每个变量分配给与所述变量同时使用的一些其他变量的多个寄存器中的一个不同的寄存器; 分配优先级获取部分，其优先级获得指示分配了多个寄存器中的每个变量的哪个寄存器的分配优先级; 以及寄存器分配部分，其根据基于分配优先级选择的分配序列将变量分配给寄存器。

82. 发明授权

US07979853B2 Compiler device, method, program and recording medium 失效
标题翻译：编译器装置，方法，程序和记录介质
公开(公告)号：US07979853B2
公开(公告)日：2011-07-12
申请号：US12019446
申请日：2008-01-24
申请人： Motohiro Kawahito , Hideaki Komatsu
发明人： Motohiro Kawahito , Hideaki Komatsu
IPC分类号： G06F9/45
CPC分类号： G06F8/41
摘要： Compiler device optimizes a program by changing an order of executing instructions. The device includes: a replaceability determination unit which determines whether a first instruction included in a first instruction sequence and a second instruction included in a second instruction sequence executed after the first instruction sequence can be replaced with a common processing instruction group including a common processing instruction for processing at least respective parts of processings by the first and second instructions together; a common processing instruction group generation unit which generates a common processing instruction group in the first instruction sequence, in place of the first instruction, when the replaceability determination unit determines the first and second instructions to be replaceable; and an instruction insertion unit which inserts the second instruction into a third instruction sequence that is an instruction sequence other than the first instruction sequence and is executed before the second instruction sequence.
摘要翻译：编译器设备通过更改执行指令的顺序来优化程序。该装置包括：可替换性确定单元，其确定包括在第一指令序列中的第一指令和包括在第一指令序列之后执行的第二指令序列中的第二指令是否可以被包括公共处理指令的公共处理指令组替换用于通过第一和第二指令一起处理至少相应的处理部分; 当可替换性确定单元确定可替换的第一和第二指令时，代替第一指令，生成第一指令序列中的公共处理指令组的公共处理指令组生成单元; 以及指令插入单元，其将第二指令插入作为第一指令序列以外的指令序列的第三指令序列，并且在第二指令序列之前执行。

83. 发明授权

US07950005B2 Method and apparatus for performing versioning for loop, method and apparatus for collecting array range check information in basic blocks, method for modifying array range check information, method for optimizing array range checks, method for generating codes for array range checks, method and apparatus for eliminating redundant array range checks, method for selecting array range checks, method for modifying array range checks, method for collecting array range checks, and method for determining handling of array range checks 失效
标题翻译：用于执行循环的方法和装置，用于收集基本块中的阵列范围检查信息的方法和装置，用于修改阵列范围检查信息的方法，用于优化阵列范围检查的方法，用于生成阵列范围检查的代码的方法，方法和装置消除冗余阵列范围检查，选择阵列范围检查的方法，修改阵列范围检查的方法，采集数组范围检查的方法以及确定数组范围检查处理的方法
公开(公告)号：US07950005B2
公开(公告)日：2011-05-24
申请号：US11838734
申请日：2007-08-14
申请人： Motohiro Kawahito , Toshiaki Yasue , Hideaki Komatsu
发明人： Motohiro Kawahito , Toshiaki Yasue , Hideaki Komatsu
IPC分类号： G06F9/44
CPC分类号： G06F8/437 , G06F8/4441
摘要： A system and method are provided that in one aspect eliminate redundant array range checks by performing a versioning for a loop. In another aspect, a system and method optimize array range checks by performing data-flow analysis in reverse order of the program execution. Yet in another aspect, a system and method obtains information about array ranges already checked by performing data-flow analysis in program execution order and eliminate redundant array range checks from this information.
摘要翻译：提供了一种系统和方法，其一方面通过执行循环的版本控制来消除冗余阵列范围检查。在另一方面，系统和方法通过以与程序执行相反的顺序执行数据流分析来优化阵列范围检查。另一方面，系统和方法通过以程序执行顺序执行数据流分析获得已经检查的数组范围的信息，并从该信息中消除冗余阵列范围检查。

84. 发明申请

US20110015916A1 SIMULATION METHOD, SYSTEM AND PROGRAM 有权
标题翻译：模拟方法，系统和程序
公开(公告)号：US20110015916A1
公开(公告)日：2011-01-20
申请号：US12834081
申请日：2010-07-12
申请人： Masaki Kataoka , Hideaki Komatsu , Goh Kondoh , Fumitomo Ohsawa
发明人： Masaki Kataoka , Hideaki Komatsu , Goh Kondoh , Fumitomo Ohsawa
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F17/5095
摘要： A simulation system having multiple peripherals that communicate with each other. The system includes a weighted graph with weights set as communication times. The peripherals are represented as nodes and connection paths are represented as edges. Among the communication times in the loop, the minimum time is set as first synchronization timing. Timing with an acceptable delay added is set as second synchronization timing. Timing set by a user to be longer than the first and second timings is set as third synchronization timing. The third synchronization timing is used in a portion where the timing is usable, thus synchronizing the peripherals at the longest possible synchronization timing.
摘要翻译：具有彼此通信的多个外围设备的模拟系统。该系统包括权重设置为通信时间的加权图。外围设备表示为节点，连接路径表示为边。在循环中的通信时间中，将最小时间设置为第一同步定时。具有可接受延迟的定时被设置为第二同步定时。由用户设定为比第一和第二定时长的定时被设定为第三同步定时。第三同步定时用于定时可用的部分，从而在尽可能长的同步定时同步外设。

85. 发明申请

US20100005457A1 METHOD OF REDUCING LOGGING CODE IN A COMPUTING SYSTEM 失效
标题翻译：降低计算系统中记录码的方法
公开(公告)号：US20100005457A1
公开(公告)日：2010-01-07
申请号：US12168206
申请日：2008-07-07
申请人： Hideaki Komatsu , Takuya Nakaike , Rei Odaira
发明人： Hideaki Komatsu , Takuya Nakaike , Rei Odaira
IPC分类号： G06F9/45
CPC分类号： G06F8/4435 , G06F8/443
摘要： A computing system for reducing logging code includes a virtual machine configured to control the flow of operations in the computing system and a compiler configured to receive bytecode instructions from the virtual machine and convert the bytecode instructions into machine instructions. The computing system also includes a compilation store configured to receive and store the machine instructions from the compiler and a recompilation store configured to receive and store recompiled machine instructions from the compiler. The system also includes a software transactional memory engine configured to receive instructions from the compilation store or, in the event that the recompilation store has recompiled machine instructions stored therein, from the recompilation store.
摘要翻译：用于减少日志记录代码的计算系统包括配置成控制计算系统中的操作流的虚拟机以及被配置为从虚拟机接收字节码指令并将该字节代码指令转换为机器指令的编译器。计算系统还包括配置存储器，其被配置为从编译器接收和存储机器指令，并且重新编译存储器被配置为从编译器接收和存储重新编译的机器指令。该系统还包括被配置为从重新编译存储器接收来自编译存储器的指令的软件事务内存引擎，或者在重新编译存储器已经重新编译存储在其中的机器指令的情况下。

86. 发明申请

US20090064112A1 TECHNIQUE FOR ALLOCATING REGISTER TO VARIABLE FOR COMPILING 失效
标题翻译：将注册分配给可编辑的变更技术
公开(公告)号：US20090064112A1
公开(公告)日：2009-03-05
申请号：US12133349
申请日：2008-06-04
申请人： Tatsushi Inagaki , Hideaki Komatsu , Takuya Nakaike , Rei Odaira
发明人： Tatsushi Inagaki , Hideaki Komatsu , Takuya Nakaike , Rei Odaira
IPC分类号： G06F9/45
CPC分类号： G06F8/441
摘要： The present invention relates to allocating registers to variables in order to compile a program. In an embodiment of the present invention a compiler apparatus stores interference information indicating an interference relationship between variables, selects a register and allocates the register to each variables in accordance with a predetermined procedure, without allocating the same register to a set of variables having interference relationships. The compiler further replaces multiple variables having the same register allocated thereto with a new variable and generates an interference relationship by merging the interference relationships each concerning one of multiple variables. The compiler further updates interference information according to the generated interference relationship and allocates to each variable in the program using the new variable a register, selected in accordance with the predetermined procedure without allocating the same register to a set of variables having the interference relationships, based on the updated interference information.
摘要翻译：本发明涉及向变量分配寄存器以便编译程序。在本发明的实施例中，编译装置存储指示变量之间的干扰关系的干扰信息，选择寄存器并根据预定的过程将寄存器分配给每个变量，而不向具有干扰关系的一组变量分配相同的寄存器。编译器进一步用新的变量代替具有与其分配的相同寄存器的多个变量，并且通过合并关于多个变量之一的干扰关系来产生干扰关系。编译器根据产生的干扰关系进一步更新干扰信息，并使用新的变量将根据预定过程选择的寄存器分配给程序中的每个变量，而不将相同的寄存器分配给具有干扰关系的一组变量，关于更新的干扰信息。

87. 发明申请

US20080276256A1 Method and System for Speeding Up Mutual Exclusion 失效
标题翻译：加快相互排斥的方法和系统
公开(公告)号：US20080276256A1
公开(公告)日：2008-11-06
申请号：US12173551
申请日：2008-07-15
申请人： Takeshi Ogasawara , Akira Koseki , Hideaki Komatsu , Kiyokuni Kawachiya , Tamiya Onodera
发明人： Takeshi Ogasawara , Akira Koseki , Hideaki Komatsu , Kiyokuni Kawachiya , Tamiya Onodera
IPC分类号： G06F9/44
CPC分类号： G06F9/52 , G06F9/3004 , G06F9/30087 , G06F9/526
摘要： In a multiprocessor computer system, a lock operation is maintained with a thread using non-atomic instructions. Identifiers are assigned to each thread. Flags in conjunction with the thread identifiers are used to determine the continuity of the lock with a thread. However, in the event continuity of the lock with the thread ceases, a compare-and-swap operation is executed to reset the lock with the same thread or another thread. Similarly, in the event there has been a collision between two or more threads requesting the lock, a compare-and-swap operation is executed to assign the lock to one of the requesting threads. Accordingly, prolonged ownership of a lock operation by a thread is encouraged to mitigate use of atomic operations in granting of the lock to a non-owning thread.
摘要翻译：在多处理器计算机系统中，使用非原子指令的线程来维护锁定操作。标识符分配给每个线程。与线程标识符一起使用的标志用于确定带有线程的锁的连续性。但是，在线程的锁定的连续性停止的情况下，执行比较和交换操作以使用相同的线程或其他线程重置锁定。类似地，如果两个或多个请求锁的线程之间发生冲突，则执行比较和交换操作以将锁分配给请求线程之一。因此，鼓励延长线程锁定操作的所有权，以减轻使用原子操作来授予对非拥有线程的锁定。

88. 发明授权

US07415383B2 Compiling method, apparatus, and program 失效
标题翻译：编译方法，装置和程序
公开(公告)号：US07415383B2
公开(公告)日：2008-08-19
申请号：US11291632
申请日：2005-12-01
申请人： Takuya Nakaike , Hideaki Komatsu
发明人： Takuya Nakaike , Hideaki Komatsu
IPC分类号： G06F19/00 , G06F17/40
CPC分类号： B25B21/00 , B25B21/026 , H04L67/02 , H04L67/322
摘要： Brings response time of a Web server and the like closer to a targeted value. A controller controlling the average response time elapsed between reception by information processing apparatus of a processing request and response of information processing apparatus to the processing request. The controller including: a section for obtaining a response time goal which is a target value of the average response time; a section for calculating a predicted response time which is a predicted value of the average response time at the time point when a predetermined reference period has elapsed from setting an operation mode in the information processing apparatus, the operation mode being any of a plurality of operation modes which provide different throughputs; and a section for setting the operation mode in the information processing apparatus if predicted response time calculated by the predicted response time calculating section is less than goal.
摘要翻译：使Web服务器等的响应时间更接近目标值。控制由信息处理装置接收处理请求之间经过的平均响应时间和信息处理装置对处理请求的响应的控制器。控制器包括：用于获得作为平均响应时间的目标值的响应时间目标的部分; 用于计算预测响应时间的部分，所述预测响应时间是在从信息处理设备中的设置操作模式经过预定基准时段的时间点的平均响应时间的预测值，所述操作模式是多个操作提供不同吞吐量的模式; 以及如果由预测响应时间计算部计算出的预测响应时间小于目标，则在信息处理装置中设定操作模式的部分。

89. 发明申请

US20080184213A1 COMPILER DEVICE, METHOD, PROGRAM AND RECORDING MEDIUM 失效
标题翻译：编译器，方法，程序和记录介质
公开(公告)号：US20080184213A1
公开(公告)日：2008-07-31
申请号：US12019446
申请日：2008-01-24
申请人： Motohiro Kawahito , Hideaki Komatsu
发明人： Motohiro Kawahito , Hideaki Komatsu
IPC分类号： G06F9/45
CPC分类号： G06F8/41
摘要： Compiler device optimizes a program by changing an order of executing instructions. The device includes: a replaceability determination unit which determines whether a first instruction included in a first instruction sequence and a second instruction included in a second instruction sequence executed after the first instruction sequence can be replaced with a common processing instruction group including a common processing instruction for processing at least respective parts of processings by the first and second instructions together; a common processing instruction group generation unit which generates a common processing instruction group in the first instruction sequence, in place of the first instruction, when the replaceability determination unit determines the first and second instructions to be replaceable; and an instruction insertion unit which inserts the second instruction into a third instruction sequence that is an instruction sequence other than the first instruction sequence and is executed before the second instruction sequence.
摘要翻译：编译器设备通过更改执行指令的顺序来优化程序。该装置包括：可替换性确定单元，其确定包括在第一指令序列中的第一指令和包括在第一指令序列之后执行的第二指令序列中的第二指令是否可以被包括公共处理指令的公共处理指令组替换用于通过第一和第二指令一起处理至少相应的处理部分; 当可替换性确定单元确定可替换的第一和第二指令时，代替第一指令，生成第一指令序列中的公共处理指令组的公共处理指令组生成单元; 以及指令插入单元，其将第二指令插入作为第一指令序列以外的指令序列的第三指令序列，并且在第二指令序列之前执行。

90. 发明授权

US07406684B2 Compiler, dynamic compiler, and replay compiler 失效
标题翻译：编译器，动态编译器和重播编译器
公开(公告)号：US07406684B2
公开(公告)日：2008-07-29
申请号：US11042722
申请日：2005-01-25
申请人： Kazunori Ogata , Tamiya Onodera , Hideaki Komatsu
发明人： Kazunori Ogata , Tamiya Onodera , Hideaki Komatsu
IPC分类号： G06F9/45
CPC分类号： G06F11/3612 , G06F9/45516 , G06F11/3636
摘要： The same executable instruction stream as an executable instruction stream generated by a dynamic compiler is reproduced to facilitate debugging of the dynamic compiler. Provides compiler program for computer functioning as: an execution status obtaining section for obtaining an execution status of the program; a dynamic compilation section for compiling one of the partial programs to be executed during execution of the program; an execution status recording section for recording the execution status in a memory area allocated on a memory of the computer; a file reading section for reading a file containing contents of the memory area allocated on the memory; and a replay compilation section for compiling the one partial program on the basis of the execution status obtained from the file to generate the same executable instruction stream as the executable instruction stream generated by the dynamic compilation section during the execution of the program.
摘要翻译：与动态编译器生成的可执行指令流相同的可执行指令流被复制以便于动态编译器的调试。提供用于计算机功能的编译器程序：执行状态获取部分，用于获取程序的执行状态; 用于编译在程序执行期间执行的部分程序之一的动态编译部分; 执行状态记录部分，用于将执行状态记录在分配在计算机的存储器上的存储区域中; 用于读取包含分配在存储器上的存储区域的内容的文件的文件读取部分; 以及重放编辑部分，用于根据从文件获得的执行状态来编译一个部分程序，以在程序执行期间生成与由动态编译部分生成的可执行指令流相同的可执行指令流。

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