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81. 发明授权

US5321646A Layout of a semiconductor memory device 失效
标题翻译：半导体存储器件的布局
公开(公告)号：US5321646A
公开(公告)日：1994-06-14
申请号：US865142
申请日：1992-04-08
申请人： Shigeki Tomishima , Mikio Asakura , Kazutami Arimoto , Hideto Hidaka , Masanori Hayashikoshi
发明人： Shigeki Tomishima , Mikio Asakura , Kazutami Arimoto , Hideto Hidaka , Masanori Hayashikoshi
IPC分类号： G11C11/409 , G11C5/14 , G11C7/06 , G11C11/401 , G11C11/4074 , G11C5/02 , G11C8/00
CPC分类号： G11C11/4074 , G11C5/14 , G11C7/065
摘要： A power supply line is disposed parallel to a sense amplifier train including a plurality of sense amplifiers at the side of each subarray. The power supply line is connected to the sense amplifier included in the sense amplifier train via a plurality of drive transistors and a sense amplifier drive line.
摘要翻译：电源线平行于包括在每个子阵列一侧的多个读出放大器的读出放大器串列布置。电源线通过多个驱动晶体管和读出放大器驱动线路连接到包括在读出放大器列中的读出放大器。

82. 发明授权

US5103426A Decoding circuit and method for functional block selection 失效
标题翻译：解码电路和功能块选择方法
公开(公告)号：US5103426A
公开(公告)日：1992-04-07
申请号：US528511
申请日：1990-05-25
申请人： Hideto Hidaka , Kazuyasu Fujishima , Yoshio Matsuda
发明人： Hideto Hidaka , Kazuyasu Fujishima , Yoshio Matsuda
IPC分类号： H01L21/82 , G11C5/06 , G11C8/00 , G11C8/12 , G11C11/401 , G11C29/00 , H01L21/822 , H01L27/04 , H01L27/10 , H03M7/00 , H03M7/22
CPC分类号： G11C8/12 , G11C5/066 , G11C29/006
摘要： An address decoding circuit for a functional block comprises branch portions serially connected with each other, in which a selecting signal is outputted on one of two output portions in accordance with the first bit information of an address signal when a selecting signal is applied to the first stage branch portion. The second stage output portion, to which the selecting signal is applied, outputs a selecting signal on one of two output portions in response to the second bit information of the address signal, in accordance with the selecting signal. Thereafter, each branch portion of the third to last stages outputs a selecting signal on one of two output portions in response to respective contents of the third bit to last bit of the address signal in accordance with the selecting signal applied from the preceding stage. By this selecting signal, a memory cell as a functional block portion is selected and is activated.

83. 发明授权

US5079748A Dynamic random access memory with read-write signal of shortened duration 失效
标题翻译：动态随机访问存储器，具有读写信号的短时间
公开(公告)号：US5079748A
公开(公告)日：1992-01-07
申请号：US469125
申请日：1990-01-24
申请人： Hideshi Miyatake , Masaki Kumanoya , Hideto Hidaka , Hiroyuki Yamasaki , Yasuhiro Konishi , Yuto Ikeda
发明人： Hideshi Miyatake , Masaki Kumanoya , Hideto Hidaka , Hiroyuki Yamasaki , Yasuhiro Konishi , Yuto Ikeda
IPC分类号： G11C11/409 , G11C11/401 , G11C11/4076 , G11C11/417 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： G11C11/4076
摘要： A semiconductor dynamic RAM provided with an I/O load (5) rendered inactive during a writing cycle comprises a monostable multivibrator (16) for receiving a read/write indicating signal W for indicating reading and writing data from and into a memory cell (2) and outputting a signal We having a shorter duration than that of the signal W at down edge of the signal W as a trigger. The output signal We of the monostable multivibrator (16) is supplied as a control signal for rendering the I/O load (5) inactive.

84. 发明授权

US4719597A Driving circuit for a shared sense amplifier with increased speed clock generation circuit for reading addressed memory cells 失效
标题翻译：用于共享读出放大器的驱动电路，具有用于读取寻址的存储器单元的增加的速度时钟产生
公开(公告)号：US4719597A
公开(公告)日：1988-01-12
申请号：US766279
申请日：1985-08-16
申请人： Masaki Kumanoya , Kazuyasu Fujishima , Hideshi Miyatake , Hideto Hidaka , Katsumi Dosaka
发明人： Masaki Kumanoya , Kazuyasu Fujishima , Hideshi Miyatake , Hideto Hidaka , Katsumi Dosaka
IPC分类号： G11C11/407 , G11C7/06 , G11C7/22 , G11C11/401 , G11C11/409 , G11C7/00 , G11C7/02 , G11C8/00
CPC分类号： G11C7/22 , G11C7/06
摘要： A cut-off clock .phi..sub.5 generated by a cut-off clock generation circuit PG is supplied to a decode circuit DEC. The decode circuit DEC decodes the cut-off clock .phi..sub.5 to produce two types of cut-off clocks .phi..sub.5L and .phi..sub.5R. The two types of cut-off clocks .phi..sub.5L and .phi..sub.5R are supplied to a control clock generation circuit as shown in FIG. 3 or 11, which in turn produces control clocks .phi..sub.2L and .phi..sub.2R. The control clocks .phi..sub.2L and .phi..sub.2R are supplied to a shared sense amplifier of FIG. 1, to control on-off operations of transfer transistors 7.sub.L, 8.sub.L, 7.sub.R and 8.sub.R.
摘要翻译：由截止时钟产生电路PG产生的截止时钟phi 5被提供给解码电路DEC。解码电路DEC解码截止时钟phi 5以产生两种类型的截止时钟phi 5L和phi 5R。两种类型的截止时钟phi 5L和phi 5R被提供给如图5所示的控制时钟产生电路。 3或11，其又产生控制时钟phi 2L和phi 2R。控制时钟phi 2L和phi 2R被提供给图1的共享读出放大器。以控制传输晶体管7L，8L，7R和8R的导通截止操作。

85. 发明授权

US07486549B2 Thin film magnetic memory device having redundant configuration 失效
标题翻译：具有冗余配置的薄膜磁存储器件
公开(公告)号：US07486549B2
公开(公告)日：2009-02-03
申请号：US11822784
申请日：2007-07-10
申请人： Hideto Hidaka
发明人： Hideto Hidaka
IPC分类号： G11C11/14 , G11C11/15 , G11C5/06 , G11C11/00 , G11C7/00 , G11C7/02
CPC分类号： G11C11/16 , G11C29/24 , G11C29/804 , G11C29/816 , G11C29/848
摘要： Normal memory cells are arranged in rows and columns, and dummy memory cells are arranged to form dummy memory cell rows by sharing memory cell columns with the normal memory cells. When there is at least one defect in the normal memory cells and/or the dummy memory cells, replacement/repair is carried out using a redundant column in a unit of memory cell column. The redundant column includes not only spare memory cells for repair of the normal memory cells but also spare dummy memory cells for repair of the dummy memory cells.
摘要翻译：正常存储单元被排列成行和列，并且通过与正常存储单元共享存储单元列来布置虚拟存储器单元以形成伪存储单元行。当正常存储器单元和/或虚拟存储单元中存在至少一个缺陷时，使用存储单元列单元中的冗余列来执行替换/修复。冗余列不仅包括用于修复正常存储器单元的备用存储单元，还包括用于修复虚拟存储器单元的备用虚拟存储器单元。

86. 发明授权

US07436717B2 Semiconductor device having mechanism capable of high-speed operation 失效
标题翻译：具有能够高速运转的机构的半导体装置
公开(公告)号：US07436717B2
公开(公告)日：2008-10-14
申请号：US10898969
申请日：2004-07-27
申请人： Hideto Hidaka
发明人： Hideto Hidaka
IPC分类号： G11C7/00
CPC分类号： G11C7/06 , G11C7/12 , G11C7/18
摘要： A semiconductor device comprises a memory cell block and a sense amplifier zone. A selection gate included in the sense amplifier zone is turned on for selectively coupling the memory cell block with the sense amplifier zone. Local drivers are dispersively arranged on a BLI wire transmitting a gate control signal, and a driver is arranged on an end of the BLI wire. The driver pulls down the potential of the BLI wire at a high speed.
摘要翻译：半导体器件包括存储器单元块和读出放大器区域。包括在感测放大器区域中的选择栅极导通，以便将存储器单元块与读出放大器区域选择性地耦合。本地驱动器分散布置在传输门控制信号的BLI线上，并且驱动器布置在BLI线的一端。驾驶员以高速拉下BLI线的电位。

87. 发明申请

US20080225622A1 SEMICONDUCTOR MEMORY DEVICE, OPERATIONAL PROCESSING DEVICE AND STORAGE SYSTEM 有权
标题翻译：半导体存储器件，操作处理器件和存储系统
公开(公告)号：US20080225622A1
公开(公告)日：2008-09-18
申请号：US12125733
申请日：2008-05-22
申请人： Hideto Hidaka
发明人： Hideto Hidaka
IPC分类号： G11C8/00
CPC分类号： G11C11/005
摘要： A thin film magnetic memory includes a size-variable Read Only Memory (ROM) region and a size-variable Random Access Memory (RAM) coupled to different ports for parallel access to the ports, respectively. A memory system allowing fast and efficient data transfer can be achieved.
摘要翻译：薄膜磁存储器包括大小可变只读存储器（ROM）区域和耦合到不同端口的大小可变随机存取存储器（RAM），用于并行地访问端口。可以实现快速高效的数据传输的存储器系统。

88. 发明申请

US20080122479A1 Low power consumption mis semiconductor device 有权
标题翻译：低功耗半导体器件
公开(公告)号：US20080122479A1
公开(公告)日：2008-05-29
申请号：US12010427
申请日：2008-01-24
申请人： Hideto Hidaka
发明人： Hideto Hidaka
IPC分类号： H03K17/16
CPC分类号： G11C5/147 , H01L27/0922 , H03K19/0016
摘要： A logic gate is constructed of an insulated gate field effect transistor (MIS transistor) having a thin gate insulation film. An operation power supply line to the logic gate is provided with an MIS transistor having a thick gate insulation film for switching the supply and stop of an operation power source voltage. A voltage of the gate of the power source switching transistor is made changing in an amplitude greater than an amplitude of an input and an output signal to the logic gate. Current consumption in a semiconductor device configured of MIS transistor of a thin gate insulation film can be reduced and an power source voltage thereof can be stabilized.
摘要翻译：逻辑门由具有薄栅绝缘膜的绝缘栅场效应晶体管（MIS晶体管）构成。提供到逻辑门的操作电源线设置有具有用于切换供电和停止操作电源电压的厚栅极绝缘膜的MIS晶体管。使电源开关晶体管的栅极的电压以大于输入的幅度和输出信号的幅度变化为逻辑门。可以减小由薄栅绝缘膜的MIS晶体管构成的半导体器件中的电流消耗，并且其电源电压可以稳定。

89. 发明授权

US07355455B2 Low power consumption MIS semiconductor device 有权
标题翻译：低功耗MIS半导体器件
公开(公告)号：US07355455B2
公开(公告)日：2008-04-08
申请号：US11369852
申请日：2006-03-08
申请人： Hideto Hidaka
发明人： Hideto Hidaka
IPC分类号： H03K19/20 , G05F1/10
CPC分类号： G11C5/147 , H01L27/0922 , H03K19/0016
摘要： A logic gate is constructed of an insulated gate field effect transistor (MIS transistor) having a thin gate insulation film. An operation power supply line to the logic gate is provided with an MIS transistor having a thick gate insulation film for switching the supply and stop of an operation power source voltage. A voltage of the gate of the power source switching transistor is made changing in an amplitude greater than an amplitude of an input and an output signal to the logic gate. Current consumption in a semiconductor device configured of MIS transistor of a thin gate insulation film can be reduced and an power source voltage thereof can be stabilized.
摘要翻译：逻辑门由具有薄栅绝缘膜的绝缘栅场效应晶体管（MIS晶体管）构成。提供到逻辑门的操作电源线设置有具有用于切换供电和停止操作电源电压的厚栅极绝缘膜的MIS晶体管。使电源开关晶体管的栅极的电压以大于输入的幅度和输出信号的幅度变化为逻辑门。可以减小由薄栅绝缘膜的MIS晶体管构成的半导体器件中的电流消耗，并且其电源电压可以稳定。

90. 发明申请

US20080037315A1 Thin film magnetic memory device writing data with bidirectional current 有权
标题翻译：薄膜磁存储器件用双向电流写入数据
公开(公告)号：US20080037315A1
公开(公告)日：2008-02-14
申请号：US11907168
申请日：2007-10-10
申请人： Hideto Hidaka
发明人： Hideto Hidaka
IPC分类号： G11C11/00
CPC分类号： G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： An end of a selected bit line in a selected column is electrically coupled to an end of a corresponding current return line by one of first and second write column select gates, which are selectively turned on in response to results of column selection. A data write circuit sets the other end of the selected bit line and the other end of the current return line to one and the other of a power supply voltage and a ground voltage in accordance with a level of write data via one of first and second data buses and an inverted data bus, respectively.
摘要翻译：所选列中的所选位线的一端通过第一和第二写列选择栅中的一个电耦合到对应的电流返回线的一端，这些选择栅根据列选择的结果选择性地导通。数据写入电路根据写入数据的电平，将所选位线的另一端和当前返回线的另一端设置为电源电压和接地电压的另一端，经由第一和第二数据总线和反相数据总线。

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