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81. 发明授权

US08415799B2 Dual damascene interconnect in hybrid dielectric 有权
标题翻译：混合电介质中的双镶嵌互连
公开(公告)号：US08415799B2
公开(公告)日：2013-04-09
申请号：US11172442
申请日：2005-06-30
申请人： Yi-Nien Su , Jyu-Horng Shieh , Hun-Jan Tao
发明人： Yi-Nien Su , Jyu-Horng Shieh , Hun-Jan Tao
IPC分类号： H01L23/48
CPC分类号： H01L21/76829 , H01L21/76808 , H01L21/7681 , H01L21/76832 , H01L21/76834 , H01L21/76835
摘要： A semiconductor device. A diffusion barrier layer overlies a substrate. An adhesion promoting layer overlies the diffusion barrier layer. A first dielectric layer between the diffusion barrier layer and the adhesion promoting layer comprises at least one via opening through the diffusion barrier layer and the adhesion promoting layer. A second dielectric layer overlies the adhesion promoting layer, comprising a trench opening above the via opening. A metal interconnect fills the via and trench openings.
摘要翻译：半导体器件。扩散阻挡层覆盖在基底上。粘附促进层覆盖在扩散阻挡层上。扩散阻挡层和增粘层之间的第一电介质层包括穿过扩散阻挡层和粘合促进层的至少一个通孔。第二电介质层覆盖粘附促进层，包括在通孔开口上方的沟槽开口。金属互连件填充通孔和沟槽开口。

82. 发明授权

US08283222B2 Method to form a semiconductor device having gate dielectric layers of varying thickness 有权
标题翻译：形成具有不同厚度的栅极电介质层的半导体器件的方法
公开(公告)号：US08283222B2
公开(公告)日：2012-10-09
申请号：US13215658
申请日：2011-08-23
申请人： Kuang-Yuan Hsu , Da-Yuan Lee , Wei-Yang Lee , Hun-Jan Tao
发明人： Kuang-Yuan Hsu , Da-Yuan Lee , Wei-Yang Lee , Hun-Jan Tao
IPC分类号： H01L21/338
CPC分类号： H01L21/823857 , H01L21/82345 , H01L21/823462 , H01L21/823842 , H01L29/513 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： A method for fabricating an integrated circuit device is disclosed which includes providing a substrate having first, second, and third regions; and forming first, second, and third gate structures in the first, second, and third regions, respectively. The first, second, and third gate structures include a gate dielectric layer, the gate dielectric layer being a first thickness in the first gate structure, a second thickness in the second gate structure, and a third thickness in the third gate structure. Forming the gate dielectric layer of the first, second, and third thicknesses can include forming an etching barrier layer over the gate dielectric layer in at least one of the first, second, or third regions while forming the first, second, and third gate structures, and/or prior to forming the gate dielectric layer in at least one of the first, second, or third regions, performing an implantation process on the at least one region.
摘要翻译：公开了一种用于制造集成电路器件的方法，其包括提供具有第一，第二和第三区域的衬底; 以及分别在第一，第二和第三区域中形成第一，第二和第三栅极结构。第一，第二和第三栅极结构包括栅极介电层，栅极电介质层是第一栅极结构中的第一厚度，第二栅极结构中的第二厚度，以及第三栅极结构中的第三厚度。形成第一，第二和第三厚度的栅介质层可以包括在形成第一，第二和第三栅极结构的至少一个第一，第二或第三区域中的栅极电介质层上方形成蚀刻阻挡层，和/或在第一，第二或第三区域中的至少一个中形成栅介质层之前，在至少一个区域上执行注入工艺。

83. 发明授权

US08202776B2 Method for protecting a gate structure during contact formation 有权
标题翻译：在接触形成期间保护栅极结构的方法
公开(公告)号：US08202776B2
公开(公告)日：2012-06-19
申请号：US12428011
申请日：2009-04-22
申请人： Hong-Dyi Chang , Pei-Chao Su , Kong-Beng Thei , Hun-Jan Tao , Harry Hak-Lay Chuang
发明人： Hong-Dyi Chang , Pei-Chao Su , Kong-Beng Thei , Hun-Jan Tao , Harry Hak-Lay Chuang
IPC分类号： H01L21/8238
CPC分类号： H01L29/78 , H01L21/28247 , H01L21/823828 , H01L21/823871 , H01L23/485 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a semiconductor device is disclosed. The method includes providing a substrate; forming at least one gate structure over the substrate; forming a plurality of doped regions in the substrate; forming an etch stop layer over the substrate; removing a first portion of the etch stop layer, wherein a second portion of the etch stop layer remains over the plurality of doped regions; forming a hard mask layer over the substrate; removing a first portion of the hard mask layer, wherein a second portion of the hard mask layer remains over the at least one gate structure; and forming a first contact through the second portion of the hard mask layer to the at least one gate structure, and a second contact through the second portion of the etch stop layer to the plurality of doped regions.
摘要翻译：公开了一种制造半导体器件的方法。该方法包括提供基板; 在所述衬底上形成至少一个栅极结构; 在所述衬底中形成多个掺杂区域; 在衬底上形成蚀刻停止层; 去除所述蚀刻停止层的第一部分，其中所述蚀刻停止层的第二部分保留在所述多个掺杂区域上; 在衬底上形成硬掩模层; 去除所述硬掩模层的第一部分，其中所述硬掩模层的第二部分保留在所述至少一个栅极结构上; 以及通过所述硬掩模层的所述第二部分形成到所述至少一个栅极结构的第一接触，以及通过所述蚀刻停止层的所述第二部分到所述多个掺杂区域的第二接触。

84. 发明授权

US08148270B2 Low K dielectric surface damage control 有权
标题翻译：低K电介质表面损伤控制
公开(公告)号：US08148270B2
公开(公告)日：2012-04-03
申请号：US12727338
申请日：2010-03-19
申请人： Hun-Jan Tao , Ryan Chia-Jen Chen , Mong-Song Liang
发明人： Hun-Jan Tao , Ryan Chia-Jen Chen , Mong-Song Liang
IPC分类号： H01L21/302
CPC分类号： H01L21/31116 , H01L21/76802 , H01L21/76807
摘要： A method of removing a silicon nitride or a nitride-based bottom etch stop layer in a copper damascene structure by etching the bottom etch stop layer is disclosed, with the method using a high density, high radical concentration plasma containing fluorine and oxygen to minimize back sputtering of copper underlying the bottom etch stop layer and surface roughening of the low-k interlayer dielectric caused by the plasma.
摘要翻译：公开了一种通过蚀刻底部蚀刻停止层去除铜镶嵌结构中的氮化硅或氮化物基底部蚀刻停止层的方法，该方法使用含有氟和氧的高密度，高自由基浓度等离子体来最小化背面底层蚀刻停止层下面的铜的溅射以及由等离子体引起的低k层间电介质的表面粗糙化。

85. 发明授权

US07834389B2 Triangular space element for semiconductor device 有权
标题翻译：半导体器件三角形空间元件
公开(公告)号：US07834389B2
公开(公告)日：2010-11-16
申请号：US11763566
申请日：2007-06-15
申请人： Yu-Lien Huang , Yi-Chen Huang , Jim Cy Huang , Weng Chang , Hun-Jan Tao
发明人： Yu-Lien Huang , Yi-Chen Huang , Jim Cy Huang , Weng Chang , Hun-Jan Tao
IPC分类号： H01L29/788
CPC分类号： H01L21/823425 , H01L21/823468 , Y10S438/981
摘要： Provided is a semiconductor device including a substrate. A gate formed on the substrate. The gate includes a sidewall. A spacer formed on the substrate and adjacent the sidewall of the gate. The spacer has a substantially triangular geometry. A contact etch stop layer (CESL) is formed on the first gate and the first spacer. The thickness of the CESL to the width of the first spacer is between approximately 0.625 and 16.
摘要翻译：提供了包括基板的半导体器件。形成在基板上的栅极。门包括侧壁。在衬底上形成并且邻近门的侧壁的间隔物。间隔件具有基本上三角形的几何形状。在第一栅极和第一间隔物上形成接触蚀刻停止层（CESL）。 CESL的厚度与第一间隔件的宽度在大约0.625和16之间。

86. 发明申请

US20100173499A1 LOW K DIELECTRIC SURFACE DAMAGE CONTROL 有权
标题翻译：低K电介质表面损伤控制
公开(公告)号：US20100173499A1
公开(公告)日：2010-07-08
申请号：US12727338
申请日：2010-03-19
申请人： Hun-Jan Tao , Ryan Chia-Jen Chen , Mong-Song Liang
发明人： Hun-Jan Tao , Ryan Chia-Jen Chen , Mong-Song Liang
IPC分类号： H01L21/306
CPC分类号： H01L21/31116 , H01L21/76802 , H01L21/76807
摘要： A method of removing a silicon nitride or a nitride-based bottom etch stop layer in a copper damascene structure by etching the bottom etch stop layer is disclosed, with the method using a high density, high radical concentration plasma containing fluorine and oxygen to minimize back sputtering of copper underlying the bottom etch stop layer and surface roughening of the low-k interlayer dielectric caused by the plasma.
摘要翻译：公开了一种通过蚀刻底部蚀刻停止层去除铜镶嵌结构中的氮化硅或氮化物基底部蚀刻停止层的方法，该方法使用含有氟和氧的高密度，高自由基浓度等离子体来最小化背面底层蚀刻停止层下面的铜的溅射以及由等离子体引起的低k层间电介质的表面粗糙化。

87. 发明授权

US07465634B2 Method of forming integrated circuit devices having n-MOSFET and p-MOSFET transistors with elevated and silicided source/drain structures 有权
公开(公告)号：US07465634B2
公开(公告)日：2008-12-16
申请号：US11583500
申请日：2006-10-18
申请人： Peng-Soon Lim , Yong-Tian Hou , Jin Ying , Hun-Jan Tao
发明人： Peng-Soon Lim , Yong-Tian Hou , Jin Ying , Hun-Jan Tao
IPC分类号： H01L21/336
CPC分类号： H01L21/823814 , H01L21/28097 , H01L21/823807 , H01L29/66636 , H01L29/7848
摘要： An n-FET and a p-FET each have elevated source/drain structures. Optionally, the p-FET elevated-SOURCE/DRAIN structure is epitaxially grown from a p-FET recess formed in the substrate. Optionally, the n-FET elevated-SOURCE/DRAIN structure is epitaxially grown from an n-FET recess formed in the substrate. The n-FET and p-FET elevated-source/drain structures are both silicided, even though the structures may have different materials and/or different structure heights. At least a thermal treatment portion of the source/drain structure siliciding is performed simultaneously for the n-FET and p-FET elevated source/drain structures. Also, the p-FET gate electrode, the n-FET gate electrode, or both, may optionally be silicided simultaneously (same metal and/or same thermal treatment step) with the n-FET and p-FET elevated-source/drain structures, respectively; even though the gate electrodes may have different materials, different silicide metal, and/or different electrode heights. The silicides formed on n-FET and p-FET elevated-source/drain structures preferably do not extend below a top surface of the substrate more than about 250 angstroms; and the structure heights may be selected to provide this.

88. 发明授权

US07400401B2 Measuring low dielectric constant film properties during processing 有权
标题翻译：在加工期间测量低介电常数膜性能
公开(公告)号：US07400401B2
公开(公告)日：2008-07-15
申请号：US11096049
申请日：2005-03-31
申请人： Jang-Shiang Tsai , Peng-Fu Hsu , Baw-Ching Perng , Ju-Wang Hsu , Jyu-Horng Shieh , Yi-Nien Su , Hun-Jan Tao
发明人： Jang-Shiang Tsai , Peng-Fu Hsu , Baw-Ching Perng , Ju-Wang Hsu , Jyu-Horng Shieh , Yi-Nien Su , Hun-Jan Tao
IPC分类号： G01J4/00
CPC分类号： G01N21/211
摘要： A method and system for determining the dielectric constant of a low-k dielectric film on a production substrate include measuring the electronic component of the dielectric constant using an ellipsometer, measuring the ionic component of the dielectric constant using an IR spectrometer, measuring the overall dielectric constant using a microwave spectrometer and deriving the dipolar component of the dielectric constant. The measurements and determination are non-contact and may be carried out on a production device that is further processed following the measurements.
摘要翻译：用于确定制造基板上的低k电介质膜的介电常数的方法和系统包括使用椭偏仪测量介电常数的电子部件，使用IR光谱仪测量介电常数的离子分量，测量总电介质使用微波光谱仪恒定并导出介电常数的偶极分量。测量和确定是非接触的，并且可以在进行测量后进一步处理的生产设备上进行。

89. 发明授权

US07390753B2 In-situ plasma treatment of advanced resists in fine pattern definition 有权
标题翻译：先进抗蚀剂的原位等离子体处理精细图案定义
公开(公告)号：US07390753B2
公开(公告)日：2008-06-24
申请号：US11274109
申请日：2005-11-14
申请人： Li-Te Lin , Yui Wang , Huan-Just Lin , Yuan-Hung Chiu , Hun-Jan Tao
发明人： Li-Te Lin , Yui Wang , Huan-Just Lin , Yuan-Hung Chiu , Hun-Jan Tao
IPC分类号： H01L21/302
CPC分类号： G03F7/40 , H01L21/0273 , H01L21/31144 , H01L21/32139
摘要： A novel, in-situ plasma treatment method for eliminating or reducing striations caused by standing waves in a photoresist mask, is disclosed. The method includes providing a photoresist mask on a BARC (bottom anti-reflective coating) layer that is deposited on a feature layer to be etched, etching the BARC layer and the underlying feature layer according to the pattern defined by the photoresist mask, and subjecting the photoresist mask to a typically argon or hydrogen bromide plasma before, after, or both before and after etching of the BARC layer prior to etching of the feature layer. Preferably, the photoresist mask is subjected to the plasma both before and after etching of the BARC layer.
摘要翻译：公开了一种用于消除或减少由光阻掩模中的驻波引起的条纹的原位等离子体处理方法。该方法包括在沉积在要蚀刻的特征层上的BARC（底部抗反射涂层）层上提供光致抗蚀剂掩模，根据由光致抗蚀剂掩模限定的图案蚀刻BARC层和下面的特征层，在蚀刻特征层之前，在蚀刻BARC层之前，之后或之后的光刻胶掩模至典型的氩或溴化氢等离子体。优选地，在蚀刻BARC层之前和之后，对光致抗蚀剂掩模进行等离子体处理。

90. 发明申请

US20080050879A1 METHODS OF FORMING METAL-CONTAINING GATE STRUCTURES 审中-公开
标题翻译：形成含金属结构结构的方法
公开(公告)号：US20080050879A1
公开(公告)日：2008-02-28
申请号：US11466656
申请日：2006-08-23
申请人： Cheng-Lung Hung , Peng-Fu Hsu , Jin Ying , Hun-Jan Tao
发明人： Cheng-Lung Hung , Peng-Fu Hsu , Jin Ying , Hun-Jan Tao
IPC分类号： H01L21/336
CPC分类号： H01L21/28185 , H01L21/28079 , H01L21/28194 , H01L29/4958 , H01L29/513 , H01L29/518 , H01L29/78
摘要： A method of forming a metal-containing gate includes forming a high-k dielectric layer over a substrate. A process using an oxygen-containing solution is provided to process the high-k dielectric layer. A metal-containing layer is formed over the high-k dielectric layer. The high-k dielectric layer and metal-containing layer are patterned, thereby defining a gate structure.
摘要翻译：形成含金属栅极的方法包括在衬底上形成高k电介质层。提供使用含氧溶液的方法来处理高k电介质层。在高k电介质层上形成含金属层。图案化高k电介质层和含金属层，由此限定栅极结构。

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