专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明申请

US20090298297A1 DUAL STRESS MEMORIZATION TECHNIQUE FOR CMOS APPLICATION 有权
标题翻译： CMOS应用的双应力记忆技术
公开(公告)号：US20090298297A1
公开(公告)日：2009-12-03
申请号：US12538110
申请日：2009-08-08
申请人： Thomas S. Kanarsky , Qiqing Ouyang , Haizhou Yin
发明人： Thomas S. Kanarsky , Qiqing Ouyang , Haizhou Yin
IPC分类号： H01L21/31
CPC分类号： H01L21/823807 , H01L21/823412 , H01L21/823468 , H01L21/823864 , H01L29/7843 , H01L29/7847
摘要： A stress-transmitting dielectric layer is formed on the at least one PFET and the at least one NFET. A tensile stress generating film, such as a silicon nitride, is formed on the at least one NFET by blanket deposition and patterning. A compressive stress generating film, which may be a refractive metal nitride film, is formed on the at least one PFET by a blanket deposition and patterning. An encapsulating dielectric film is deposited over the compress stress generating film. The stress is transferred from both the tensile stress generating film and the compressive stress generating film into the underlying semiconductor structures. The magnitude of the transferred compressive stress from the refractory metal nitride film may be from about 5 GPa to about 20 GPa. The stress is memorized during an anneal and remains in the semiconductor devices after the stress generating films are removed.
摘要翻译：在至少一个PFET和至少一个NFET上形成应力传导电介质层。通过毯式沉积和图案化在至少一个NFET上形成拉伸应力产生膜，例如氮化硅。可以通过覆盖沉积和图案化在至少一个PFET上形成可以是折射金属氮化物膜的压应力产生膜。在压缩应力产生膜上沉积密封电介质膜。应力从拉伸应力产生膜和压缩应力产生膜转移到下面的半导体结构中。来自难熔金属氮化物膜的转移的压缩应力的大小可以为约5GPa至约20GPa。应力在退火期间被记忆，并且在除去应力产生膜之后保留在半导体器件中。

82. 发明申请

US20080185658A1 Buried Stress Isolation for High-Performance CMOS Technology 失效
标题翻译：埋地应力隔离用于高性能CMOS技术
公开(公告)号：US20080185658A1
公开(公告)日：2008-08-07
申请号：US12099195
申请日：2008-04-08
申请人： MeiKei Ieong , Zhibin Ren , Haizhou Yin
发明人： MeiKei Ieong , Zhibin Ren , Haizhou Yin
IPC分类号： H01L27/08 , H01L21/8238
CPC分类号： H01L29/7846 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/66772 , H01L29/78654 , H01L29/78696
摘要： A field effect transistor (FET) comprises a substrate; a buried oxide (BOX) layer over the substrate; a current channel region over the BOX layer; source/drain regions adjacent to the current channel region; a buried high-stress film in the BOX layer and regions of the substrate, wherein the high-stress film comprises any of a compressive film and a tensile film; an insulating layer covering the buried high-stress film; and a gate electrode over the current channel region, wherein the high-stress film is adapted to create mechanical stress in the current channel region, wherein the high-stress film is adapted to stretch the current channel region in order to create the mechanical stress in the current channel region; wherein the mechanical stress comprises any of compressive stress and tensile stress, and wherein the mechanical stress caused by the high-stress film causes an increased charge carrier mobility in the current channel region.
摘要翻译：场效应晶体管（FET）包括衬底; 在衬底上的掩埋氧化物（BOX）层; BOX层上的当前通道区域; 源极/漏极区域与当前沟道区域相邻; BOX层中的埋置的高应力膜和衬底的区域，其中高应力膜包括任何压缩膜和拉伸膜; 覆盖埋置的高应力膜的绝缘层; 以及在电流通道区域上的栅电极，其中所述高应力膜适于在所述电流通道区域中产生机械应力，其中所述高应力膜适于拉伸所述电流通道区域，以便产生机械应力当前通道区域; 其中机械应力包括任何压缩应力和拉伸应力，并且其中由高应力膜引起的机械应力导致当前通道区域中电荷载流子迁移率增加。

83. 发明申请

US20080179627A1 Strained MOS devices using source/drain epitaxy 有权
标题翻译：使用源极/漏极外延的应变MOS器件
公开(公告)号：US20080179627A1
公开(公告)日：2008-07-31
申请号：US11669902
申请日：2007-01-31
申请人： Meikei Ieong , Xiao Hu Liu , Qiqing Christine Ouyang , Siddhartha Panda , Haizhou Yin
发明人： Meikei Ieong , Xiao Hu Liu , Qiqing Christine Ouyang , Siddhartha Panda , Haizhou Yin
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/84 , H01L29/1054 , H01L29/165 , H01L29/66636 , H01L29/7848 , H01L29/78687
摘要： NMOS and PMOS device structures with separately strained channel regions and methods of their fabrication are disclosed. The source and the drain of the NMOS device is epitaxially grown of a material which causes a shift in the strain of the NMOS device channel in the tensile direction. While, the source and the drain of the PMOS device is epitaxially grown of a material which causes a shift in the strain of the PMOS device channel in the compressive direction.
摘要翻译：公开了具有单独应变通道区域的NMOS和PMOS器件结构及其制造方法。 NMOS器件的源极和漏极由引起NMOS器件沟道在拉伸方向上的应变移动的材料外延生长。而PMOS器件的源极和漏极是外延生长的，这种材料导致PMOS器件沟道在压缩方向上的应变移动。

84. 发明授权

US09691878B2 Method of manufacturing MOSFET 有权
公开(公告)号：US09691878B2
公开(公告)日：2017-06-27
申请号：US14436892
申请日：2012-10-30
申请人： Haizhou Yin , Huilong Zhu , Changliang Qin , Huaxiang Yin
发明人： Haizhou Yin , Huilong Zhu , Changliang Qin , Huaxiang Yin
IPC分类号： H01L29/06 , H01L29/66 , H01L29/78 , H01L29/165 , H01L21/762 , H01L21/02 , H01L21/265 , H01L21/306 , H01L21/308 , H01L29/161
CPC分类号： H01L29/66636 , H01L21/02381 , H01L21/02529 , H01L21/02532 , H01L21/26513 , H01L21/30604 , H01L21/3081 , H01L21/3083 , H01L21/76224 , H01L29/0653 , H01L29/161 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/7848
摘要： Provided is a method for manufacturing a MOSFET, including: forming a shallow trench isolation (STI) in a semiconductor substrate to define an active region for the MOSFET; performing etching with the STI as a mask, to expose a surface of the semiconductor substrate, and to protrude a portion of the STI with respect to the surface of the semiconductor substrate, resulting in a protruding portion; forming a first spacer on sidewalls of the protruding portion; forming a gate stack on the semiconductor substrate; forming a second spacer surrounding the gate stack; forming openings in the semiconductor substrate with the STI, the gate stack, the first spacer and the second spacer as a mask; epitaxially growing a semiconductor layer with a bottom surface and sidewalls of each of the openings as a growth seed layer; and performing ion implantation into the semiconductor layer to form source and drain regions.

85. 发明授权

US09263581B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US09263581B2
公开(公告)日：2016-02-16
申请号：US14394802
申请日：2012-05-30
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo , Qingqing Liang
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo , Qingqing Liang
IPC分类号： H01L23/62 , H01L29/78 , H01L29/66 , H01L29/786 , H01L21/265 , H01L21/324 , H01L29/06
CPC分类号： H01L29/7849 , H01L21/265 , H01L21/26506 , H01L21/2652 , H01L21/324 , H01L29/0649 , H01L29/66545 , H01L29/66583 , H01L29/66772 , H01L29/78654
摘要： A method for manufacturing a semiconductor structure comprises the following steps: providing an SOI substrate and forming a gate structure on the SOI substrate; implanting ions to induce stress in the semiconductor structure by using the gate structure as mask to form a stress-inducing region, which is located under the BOX layer on the SOI substrate on both sides of the gate structure. A semiconductor structure manufactured according to the above method is also disclosed. The semiconductor structure and the method for manufacturing the same disclosed in the present application form on the ground layer a stress-inducing region, which provides favorable stress to the semiconductor device channel and contributes to the improvement of the semiconductor device performance.
摘要翻译：一种制造半导体结构的方法包括以下步骤：在SOI衬底上提供SOI衬底并形成栅极结构; 通过使用栅极结构作为掩模来注入离子以在半导体结构中引起应力，以形成位于栅极结构两侧的SOI衬底上的BOX层下方的应力诱导区域。还公开了根据上述方法制造的半导体结构。在本申请中公开的半导体结构及其制造方法在地层上形成应力诱导区域，其对半导体器件沟道提供有利的应力，有助于提高半导体器件的性能。

86. 发明授权

US09236384B2 Semiconductor memory device and method for accessing the same 有权
标题翻译：半导体存储器件及其访问方法
公开(公告)号：US09236384B2
公开(公告)日：2016-01-12
申请号：US14355120
申请日：2012-03-22
申请人： Zhijiong Luo , Zhengyong Zhu , Haizhou Yin , Huilong Zhu
发明人： Zhijiong Luo , Zhengyong Zhu , Haizhou Yin , Huilong Zhu
IPC分类号： G11C11/405 , G11C5/06 , G11C5/02 , G11C7/00 , H01L27/105 , G11C11/404 , H01L29/267 , H01L29/786 , G11C8/16 , H01L27/108
CPC分类号： H01L27/1052 , G11C5/06 , G11C7/00 , G11C8/16 , G11C11/404 , G11C11/405 , H01L27/108 , H01L29/267 , H01L29/7869
摘要： A semiconductor memory device and a method for accessing the same are disclosed. The semiconductor memory device comprises a memory transistor, a first control transistor and a second control transistor, wherein a source electrode and a gate electrode of the first control transistor are coupled to a first bit line and a first word line respectively, a drain electrode and a gate electrode of the second control transistor are coupled to a second word line and a second bit line respectively, a gate electrode of the memory transistor is coupled to a drain electrode of the first control transistor, a drain electrode of the memory transistor is coupled to a source electrode of the second control transistor, and a source electrode of the memory transistor is coupled to ground, and wherein the memory transistor exhibits a gate electrode-controlled memory characteristic. The semiconductor memory device increases integration level and decreases refresh frequency.
摘要翻译：公开了一种半导体存储器件及其访问方法。半导体存储器件包括存储晶体管，第一控制晶体管和第二控制晶体管，其中第一控制晶体管的源电极和栅电极分别耦合到第一位线和第一字线，漏电极和第二控制晶体管的栅电极分别耦合到第二字线和第二位线，存储晶体管的栅电极耦合到第一控制晶体管的漏电极，存储晶体管的漏电极耦合到第二控制晶体管的源电极，并且存储晶体管的源电极耦合到地，并且其中存储晶体管表现出栅电极控制的存储特性。半导体存储器件增加了集成度并降低了刷新频率。

87. 发明授权

US09178070B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US09178070B2
公开(公告)日：2015-11-03
申请号：US13138053
申请日：2011-03-04
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L27/12 , H01L29/786 , H01L29/423 , H01L29/66
CPC分类号： H01L29/78648 , H01L29/42384 , H01L29/66772 , H01L29/78603
摘要： The present application discloses a semiconductor structure and a method for manufacturing the same. A semiconductor structure according to the present invention can adjust the threshold voltage by capacitive coupling between a backgate region either and a source region or a drain region with a common contact, i.e. a source contact or a drain contact, which leads to a simple manufacturing process, a higher integration level, and a lower manufacture cost. Moreover, the asymmetric design of the backgate structure, together with the doping of the backgate region which can be varied as required in an actual device design, can further enhance the effects of adjusting the threshold voltage and improve the performances of the device.
摘要翻译：本申请公开了一种半导体结构及其制造方法。根据本发明的半导体结构可以通过在具有公共接触的源极区域或漏极区域之间的电容耦合来调节阈值电压，即源极接触或漏极接触，这导致简单的制造过程，更高的集成度，更低的制造成本。此外，背栅结构的非对称设计以及可以根据实际器件设计中所需而改变的背栅区域的掺杂，可以进一步增强调节阈值电压并提高器件性能的效果。

88. 发明授权

US08969164B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US08969164B2
公开(公告)日：2015-03-03
申请号：US14002456
申请日：2012-03-23
申请人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L21/336 , H01L29/78 , H01L29/66 , H01L29/08 , H01L21/84 , H01L27/12 , H01L21/8234 , H01L29/51
CPC分类号： H01L29/7842 , H01L21/823412 , H01L21/84 , H01L27/1203 , H01L29/0847 , H01L29/51 , H01L29/66431
摘要： A semiconductor structure comprises a substrate, a gate stack, a base area, and a source/drain region, wherein the gate stack is located on the base area, the source/drain region is located in the base area, and the base area is located on the substrate. A supporting isolated structure is provided between the base area and the substrate, wherein part of the supporting structure is connected to the substrate; a cavity is provided between the base area and the substrate, wherein the cavity is composed of the base area, the substrate and the supporting isolated structure. A stressed material layer is provided on both sides of the gate stack, the base area and the supporting isolated structure. Correspondingly, a method is provided for manufacturing such a semiconductor structure, which inhibits the short channel effect, reduces the parasitic capacitance and leakage current, and enhances the steepness of the source/drain region.
摘要翻译：半导体结构包括衬底，栅极堆叠，基极区域和源极/漏极区域，其中栅极堆叠层位于基极区域上，源极/漏极区域位于基极区域中，并且基极区域是位于基板上。在基部区域和基板之间设置支撑隔离结构，其中支撑结构的一部分连接到基板; 在基部区域和基板之间设置空腔，其中空腔由基底区域，基底和支撑隔离结构构成。在栅极堆叠的两侧，基部区域和支撑隔离结构上设置应力材料层。相应地，提供了一种用于制造这种半导体结构的方法，其抑制短沟道效应，降低寄生电容和漏电流，并且增强源/漏区的陡度。

89. 发明授权

US08828840B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08828840B2
公开(公告)日：2014-09-09
申请号：US13379546
申请日：2011-04-26
申请人： Zhijiong Luo , Huilong Zhu , Haizhou Yin
发明人： Zhijiong Luo , Huilong Zhu , Haizhou Yin
IPC分类号： H01L21/762 , H01L21/02
CPC分类号： H01L21/76232 , H01L21/02381 , H01L21/02521 , H01L21/02639 , H01L21/02647
摘要： A semiconductor device and a method for manufacturing the same are disclosed. The method comprises: forming at least one trench in a first semiconductor layer, wherein at least lower portions of respective sidewalls of the trench tilt toward outside of the trench; filling a dielectric material in the trench, thinning the first semiconductor layer so that the first semiconductor layer is recessed with respect to the dielectric material, and epitaxially growing a second semiconductor layer on the first semiconductor layer, wherein the first semiconductor layer and the semiconductor layer comprise different materials from each other. According to embodiments of the disclosure, defects occurring during the heteroepitaxial growth can be effectively suppressed.
摘要翻译：公开了一种半导体器件及其制造方法。该方法包括：在第一半导体层中形成至少一个沟槽，其中沟槽的各个侧壁的至少下部部分朝向沟槽的外侧倾斜; 在沟槽中填充介电材料，使第一半导体层变薄，使得第一半导体层相对于电介质材料凹陷，并且在第一半导体层上外延生长第二半导体层，其中第一半导体层和半导体层包括彼此不同的材料。根据本公开的实施例，可以有效地抑制在异质外延生长期间发生的缺陷。

90. 发明申请

US20140238461A1 SOLAR CELL UNIT AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：太阳能电池单元及其制造方法
公开(公告)号：US20140238461A1
公开(公告)日：2014-08-28
申请号：US13950510
申请日：2013-07-25
申请人： Zhijiong LUO , Huilong ZHU , Haizhou Yin
发明人： Zhijiong LUO , Huilong ZHU , Haizhou Yin
IPC分类号： H01L31/18 , H01L31/04
CPC分类号： H01L31/035281 , H01L31/042 , H01L31/0504 , H01L31/1804 , H01L31/202 , Y02E10/50 , Y02E10/547 , Y02P70/521
摘要： The present invention provides a solar cell unit, which comprises a semiconductor plate of first-type doping or second-type doping; wherein the semiconductor plate has a first surface and a second surface opposite to the first surface; the semiconductor plate comprises a first-type doping region and second-type doping region, both the first-type doping region and the second-type doping region are located on the first surface of the semiconductor plate; a first sheet is provided on the side surface of the semiconductor plate that is adjacent to the first-type doping region, and a second sheet is provided on the side surface of the semiconductor plate that is adjacent to the second type doping region.
摘要翻译：本发明提供一种太阳能电池单元，其包括第一种掺杂或二次掺杂的半导体板; 其中所述半导体板具有与所述第一表面相对的第一表面和第二表面; 所述半导体板包括第一类型掺杂区域和第二类型掺杂区域，所述第一类型掺杂区域和所述第二类型掺杂区域都位于所述半导体板件的所述第一表面上; 第一片设置在与第一型掺杂区相邻的半导体板的侧表面上，并且第二片设置在与第二类型掺杂区相邻的半导体板的侧表面上。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式