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81. 发明授权

US06413875B1 Process and apparatus for improving the performance of a temperature-sensitive etch process 有权
标题翻译：用于改善温度敏感蚀刻工艺性能的工艺和设备
公开(公告)号：US06413875B1
公开(公告)日：2002-07-02
申请号：US09666261
申请日：2000-09-21
申请人： Guy T. Blalock , Bradley J. Howard
发明人： Guy T. Blalock , Bradley J. Howard
IPC分类号： H01L21302
CPC分类号： H01L21/31116
摘要： The temperature of a dry etch process of a semiconductor substrate in a plasma etch chamber is controlled to maintain selectivity while also providing a high etch rate by introducing one or more cooling steps into the etch process. To maintain selectivity of the etch as well as a high rate of etch, the formation of plasma is terminated prior to exceeding a predetermined maximum temperature at at least one selected location in the chamber. The temperature at the selected location is reduced prior to the resumption of plasma flow and etching. The plasma etch is then continued, and may optionally be terminated again to permit cooling, as needed, until etching has been completed.
摘要翻译：控制等离子体蚀刻室中的半导体衬底的干蚀刻工艺的温度以保持选择性，同时通过将一个或多个冷却步骤引入到蚀刻工艺中来提供高蚀刻速率。为了保持蚀刻的选择性以及高的蚀刻速率，等离子体的形成在超过腔室中的至少一个选定位置处的预定最大温度之前终止。在等离子体流动和蚀刻恢复之前，所选位置处的温度降低。然后继续等离子体蚀刻，并且可以根据需要可选地再次终止以允许冷却，直到蚀刻完成。

82. 发明授权

US06400029B1 Self-limiting method of reducing contamination in a contact opening, method of making contacts and semiconductor devices therewith, and resulting structures 有权
标题翻译：减少接触开口中污染的自限制方法，与其接触的半导体器件的制造方法以及结构
公开(公告)号：US06400029B1
公开(公告)日：2002-06-04
申请号：US09372326
申请日：1999-08-11
申请人： Guy T. Blalock , Bradley J. Howard
发明人： Guy T. Blalock , Bradley J. Howard
IPC分类号： H01L2348
CPC分类号： H01L21/02046 , H01L21/76805 , H01L21/76814
摘要： A method of forming a contact opening including removing a residual carbon/halide layer which may form in the contact opening during the etching of the dielectric layer, or which may be intentionally deposited in the contact opening, wherein the removal of the carbon/halide layer also advantageously removes an adjacent portion of the active-device region of the semiconductor substrate which has become damaged or dopant depleted during the fabrication process. The removal of the carbon/halide layer is effected by a directional, energetic ion bombardment to activate the halides in the carbon/halide layer which, in turn, removes both the carbon/halide layer and a portion of the active-device region in a substantially anisotropic manner. The method of present invention is self-limiting because, once the halides within the carbon/halide layer are activated and thereby depleted, the removal of material in the adjacent active-device region ceases.
摘要翻译：一种形成接触开口的方法，包括去除在电介质层的蚀刻期间可能在接触开口中形成的残留的碳/卤化物层，或者可能有意沉积在接触开口中，其中去除碳/卤化物层还有利地去除在制造过程中已经损坏或掺杂物耗尽的半导体衬底的有源器件区域的相邻部分。碳/卤化物层的去除是通过定向的，高能的离子轰击来实现的，以激活碳/卤化物层中的卤化物，其又在一个或多个碳/卤化物层中除去碳/卤化物层和一部分有源器件区域基本上是各向异性的。本发明的方法是自限制的，因为一旦碳/卤化物层中的卤化物被活化并由此耗尽，则相邻活性元件区域中的材料的去除就停止。

83. 发明授权

US06391710B1 Methods of forming capacitors 有权
标题翻译：形成电容器的方法
公开(公告)号：US06391710B1
公开(公告)日：2002-05-21
申请号：US09602832
申请日：2000-06-23
申请人： John T. Moore , Guy T. Blalock , Scott Jeffrey DeBoer
发明人： John T. Moore , Guy T. Blalock , Scott Jeffrey DeBoer
IPC分类号： H01L218242
CPC分类号： H01L28/40 , H01L21/31116 , H01L21/3146 , Y10S438/924 , Y10S438/97
摘要： In one aspect, the invention includes an etching process, comprising: a) providing a first material over a substrate, the first material comprising from about 2% to about 20% carbon (by weight); b) providing a second material over the first material; and c) etching the second material at a faster rate than the first material. In another aspect, the invention includes a capacitor forming method, comprising: a) forming a wordline over a substrate; b) defining a node proximate the wordline; c.) forming an etch stop layer over the wordline, the etch stop layer comprising carbon; d) forming an insulative layer over the etch stop layer; e) etching through the insulative layer to the etch stop layer to form an opening through the insulative layer; and e) forming a capacitor construction comprising a storage node, dielectric layer and second electrode, at least a portion of the capacitor construction being within the opening. In yet another aspect, the invention includes a semiconductive material assembly, comprising: a) a semiconductive substrate; and b) a layer over the semiconductive substrate, the layer comprising silicon, nitrogen and carbon.
摘要翻译：一方面，本发明包括蚀刻工艺，其包括：a）在衬底上提供第一材料，所述第一材料包含约2％至约20％的碳（重量）; b）在第一材料上提供第二材料; 以及c）以比所述第一材料更快的速率蚀刻所述第二材料。另一方面，本发明包括电容器形成方法，包括：a）在衬底上形成字线; b）定义靠近字线的节点; c）在所述字线上形成蚀刻停止层，所述蚀刻停止层包含碳; d）在所述蚀刻停止层上形成绝缘层; e）通过绝缘层蚀刻到蚀刻停止层以形成穿过绝缘层的开口; 以及e）形成包括存储节点，电介质层和第二电极的电容器结构，所述电容器结构的至少一部分在所述开口内。在另一方面，本发明包括半导体材料组件，其包括：a）半导体衬底; 以及b）半导体衬底上的层，该层包含硅，氮和碳。

84. 发明授权

US06232219B1 Self-limiting method of reducing contamination in a contact opening, method of making contacts and semiconductor devices therewith, and resulting structures 失效
标题翻译：减少接触开口中污染的自限制方法，与其接触的半导体器件的制造方法以及结构
公开(公告)号：US06232219B1
公开(公告)日：2001-05-15
申请号：US09082138
申请日：1998-05-20
申请人： Guy T. Blalock , Bradley J. Howard
发明人： Guy T. Blalock , Bradley J. Howard
IPC分类号： H01L213065
CPC分类号： H01L21/02046 , H01L21/76805 , H01L21/76814
摘要： A method of forming a contact opening including removing a residual carbon/halide layer which may form in the contact opening during the etching of the dielectric layer, or which may be intentionally deposited in the contact opening, wherein the removal of the carbon/halide layer also advantageously removes an adjacent portion of the active-device region of the semiconductor substrate which has become damaged or dopant depleted during the fabrication process. The removal of the carbon/halide layer is effected by a directional, energetic ion bombardment to activate the halides in the carbon/halide layer which, in turn, removes both the carbon/halide layer and a portion of the active-device region in a substantially anisotropic manner. The method of present invention is self-limiting because, once the halides within the carbon/halide layer are activated and thereby depleted, the removal of material in the adjacent active-device region ceases.
摘要翻译：一种形成接触开口的方法，包括去除在电介质层的蚀刻期间可能在接触开口中形成的残留的碳/卤化物层，或者可能有意沉积在接触开口中，其中去除碳/卤化物层还有利地去除在制造过程中已经损坏或掺杂物耗尽的半导体衬底的有源器件区域的相邻部分。碳/卤化物层的去除是通过定向的，高能的离子轰击来实现的，以激活碳/卤化物层中的卤化物，其又在一个或多个碳/卤化物层中除去碳/卤化物层和一部分有源器件区域基本上是各向异性的。本发明的方法是自限制的，因为一旦碳/卤化物层中的卤化物被活化并由此耗尽，则相邻活性元件区域中的材料的去除就停止。

85. 发明授权

US06221205B1 Apparatus for improving the performance of a temperature-sensitive etch 有权
标题翻译：用于改善温度敏感蚀刻性能的装置
公开(公告)号：US06221205B1
公开(公告)日：2001-04-24
申请号：US09560089
申请日：2000-04-28
申请人： Guy T. Blalock , Bradley J. Howard
发明人： Guy T. Blalock , Bradley J. Howard
IPC分类号： H05H100
CPC分类号： H01L21/31116
摘要： The temperature of a dry etch process of a semiconductor substrate in a plasma etch chamber is controlled to maintain selectivity while also providing a high etch rate by introducing one or more cooling steps into the etch process. To maintain selectivity of the etch as well as a high rate of etch, the formation of plasma is terminated prior to exceeding a predetermined maximum temperature at at least one selected location in the chamber. The temperature at the selected location is reduced prior to the resumption of plasma flow and etching. The plasma etch is then continued, and may optionally be terminated again to permit cooling, as needed, until etching has been completed.
摘要翻译：控制等离子体蚀刻室中的半导体衬底的干蚀刻工艺的温度以保持选择性，同时通过将一个或多个冷却步骤引入到蚀刻工艺中来提供高蚀刻速率。为了保持蚀刻的选择性以及高的蚀刻速率，等离子体的形成在超过腔室中的至少一个选定位置处的预定最大温度之前终止。在等离子体流动和蚀刻恢复之前，所选位置处的温度降低。然后继续等离子体蚀刻，并且可以根据需要可选地再次终止以允许冷却，直到蚀刻完成。

86. 发明授权

US6136670A Semiconductor processing methods of forming contacts between electrically conductive materials 失效
标题翻译：在导电材料之间形成接触的半导体加工方法
公开(公告)号：US6136670A
公开(公告)日：2000-10-24
申请号：US146763
申请日：1998-09-03
申请人： Guy T. Blalock , Max Hineman
发明人： Guy T. Blalock , Max Hineman
IPC分类号： H01L21/311 , H01L21/3213 , H01L21/768 , H01L21/322 , H01L21/44 , H01L21/461
CPC分类号： H01L21/76838 , H01L21/31116 , H01L21/3213 , H01L21/76814
摘要： In one aspect, the invention includes a semiconductor processing method of forming a contact between two electrically conductive materials comprising: a) forming a first conductive material over a substrate, the first conductive material being capable of being oxidized in the presence of oxygen to an insulating material; b) sputter cleaning the first conductive material in the presence of oxygen in a gaseous phase and in the presence of an oxygen gettering agent; and c) forming a second conductive material in electrical contact with the first conductive material. In another aspect, the invention includes a semiconductor processing method of forming a contact between two metal layers comprising: a) forming a first metal layer over a substrate; b) forming an oxygen containing material over the substrate proximate the first metal layer and covering at least a portion of the first metal layer; c) forming an opening through the oxygen containing material to the first metal layer; e) after forming the opening and with the substrate in a processing chamber, sputter cleaning the first metal layer and liberating oxygen from the oxygen containing material; f) while sputter cleaning, gettering the liberated oxygen within the processing chamber; and g) forming a second metal layer within the opening and in electrical contact with the first metal layer.
摘要翻译：一方面，本发明包括一种在两种导电材料之间形成接触的半导体处理方法，包括：a）在衬底上形成第一导电材料，所述第一导电材料能够在氧气存在下被氧化成绝缘的材料; b）在氧气存在下，在气相和氧吸气剂的存在下溅射清洗第一导电材料; 以及c）形成与所述第一导电材料电接触的第二导电材料。另一方面，本发明包括在两个金属层之间形成接触的半导体处理方法，包括：a）在衬底上形成第一金属层; b）在靠近第一金属层的基底上形成含氧材料，并覆盖第一金属层的至少一部分; c）通过所述含氧材料形成通向所述第一金属层的开口; e）在处理室中形成开口和衬底之后，溅射清洗第一金属层并从含氧材料释放氧; f）同时溅射清洗，吸收处理室内释放的氧气; 以及g）在所述开口内形成第二金属层并与所述第一金属层电接触。

87. 发明授权

US6051502A Methods of forming conductive components and methods of forming conductive lines 失效
标题翻译：形成导电组件的方法和形成导电线的方法
公开(公告)号：US6051502A
公开(公告)日：2000-04-18
申请号：US953910
申请日：1997-10-20
申请人： Harlan H. Frankamp , Guy T. Blalock
发明人： Harlan H. Frankamp , Guy T. Blalock
IPC分类号： H01L21/28 , H01L21/02 , H01L21/302 , H01L21/3065 , H01L21/3213 , H01L21/311
CPC分类号： H01L21/02071
摘要： The invention encompasses methods of forming conductive components and methods of forming conductive lines. In one aspect, the invention includes a method of forming a conductive component comprising: a) anisotropically etching a conductive material into a conductive component shape having at least one sidewall, and forming an etch blocking layer over the sidewall during the anisotropic etching; and b) removing the etch blocking layer with an etchant comprising fluorine and a noble element. In another aspect, the invention includes a method of forming a conductive line comprising: a) forming a layer of conductive material; b) forming a masking layer over a portion of the layer of conductive material in the shape of a conductive line; c) anisotropically etching the conductive material with the masking layer in place to form a conductive line beneath the masking layer, the conductive line having sidewalls, a blocking layer forming over the sidewalls during the anisotropic etching; and d) removing the blocking layer with an etchant comprising fluorine and a noble element.
摘要翻译：本发明包括形成导电组件的方法和形成导电线的方法。一方面，本发明包括形成导电部件的方法，包括：a）各向异性地将导电材料蚀刻成具有至少一个侧壁的导电部件形状，并且在各向异性蚀刻期间在侧壁上形成蚀刻阻挡层; 和b）用包括氟和贵金属的蚀刻剂去除蚀刻阻挡层。另一方面，本发明包括形成导线的方法，包括：a）形成导电材料层; b）在导电线形状的导电材料层的一部分上形成掩模层; c）各向异性地蚀刻具有掩蔽层的导电材料，以在掩模层下方形成导电线，该导电线具有侧壁，在各向异性蚀刻期间在侧壁上形成阻挡层; 和d）用包括氟和贵金属的蚀刻剂去除阻挡层。

88. 发明授权

US6015760A Method for enhancing oxide to nitride selectivity through the use of independent heat control 失效
公开(公告)号：US6015760A
公开(公告)日：2000-01-18
申请号：US905891
申请日：1997-08-04
申请人： David S. Becker , Guy T. Blalock , Fred L. Roe
发明人： David S. Becker , Guy T. Blalock , Fred L. Roe
IPC分类号： H01L21/311 , H01L21/768 , H01L21/302
CPC分类号： H01L21/31116 , H01L21/76802
摘要： A process for controlling the etch of a silicon dioxide layer at a high etch rate and high selectivity with respect to silicon nitride, particularly in a multilayer structure, by maintaining various portions of the etch chamber at elevated temperatures.

89. 发明申请

US20120237165A1 RESONATOR FOR THERMO OPTIC DEVICE 有权
标题翻译：热电偶装置谐振器
公开(公告)号：US20120237165A1
公开(公告)日：2012-09-20
申请号：US13483542
申请日：2012-05-30
申请人： Gurtej Singh Sandhu , Guy T. Blalock , Howard E. Rhodes
发明人： Gurtej Singh Sandhu , Guy T. Blalock , Howard E. Rhodes
IPC分类号： G02B6/26
CPC分类号： G02B6/132 , G02B6/12004 , G02B6/12007 , G02B6/136 , G02F1/011 , G02F1/0147 , G02F2203/15
摘要： A resonator for thermo optic devices is formed in the same process steps as a waveguide and is formed in a depression of a lower cladding while the waveguide is formed on a surface of the lower cladding. Since upper surfaces of the resonator and waveguide are substantially coplanar, the aspect ratio, as between the waveguide and resonator in an area where the waveguide and resonator front one another, decreases thereby increasing the bandwidth of the resonator. The depression is formed by photomasking and etching the lower cladding before forming the resonator and waveguide. Pluralities of resonators are also taught that are formed in a plurality of depressions of the lower cladding. To decrease resonator bandwidth, waveguide(s) are formed in the depression(s) of the lower cladding while the resonator is formed on the surface. Thermo optic devices formed with these resonators are also taught.
摘要翻译：用于热光器件的谐振器以与波导相同的工艺步骤形成，并且形成在下包层的凹陷中，同时波导形成在下包层的表面上。由于谐振器和波导的上表面基本上是共面的，因此在波导和谐振器彼此前向的区域中的波导和谐振器之间的纵横比减小，从而增加了谐振器的带宽。在形成谐振器和波导之前，通过光掩模和蚀刻下部包层形成凹陷。还教导了形成在下部包层的多个凹部中的多个谐振器。为了减小谐振器带宽，当在表面上形成谐振器时，在下包层的凹陷中形成波导。还教导了用这些谐振器形成的热光器件。

90. 发明授权

US08124320B2 Method and apparatus for surface tension control in advanced photolithography 有权
标题翻译：先进光刻中表面张力控制的方法和装置
公开(公告)号：US08124320B2
公开(公告)日：2012-02-28
申请号：US11302293
申请日：2005-12-13
申请人： Guy T. Blalock
发明人： Guy T. Blalock
IPC分类号： G03F7/00 , G03F7/26 , G03F7/40
CPC分类号： H01L21/67034 , G03F7/422
摘要： A method and apparatus are used for cleaning and drying a semiconductor wafer. Within a sealable chamber, a wafer having photoresist features thereon is spun while a cleaning fluid is applied to a top surface of the semiconductor wafer to clean off excess photoresist. A rinsing solution is applied to rinse the semiconductor wafer of any remaining impurities. To reduce stresses on the photoresist features caused by surface tension of the rinsing solution as it dries, which stresses may cause toppling of the features, the semiconductor wafer is dried in a vapor ambient within the sealable chamber. The vapor ambient, formed by combining an inert gas with a vaporized surface tension modifying fluid, produces a Marangoni effect to reduce surface tension of the rinsing solution. Optionally, to further reduce surface tension, a surfactant may be introduced into the rinsing solution and the temperature and pressure of the interior of the sealed chamber may be adjusted.
摘要翻译：使用方法和装置来清洁和干燥半导体晶片。在可密封的室内，其上具有光刻胶特征的晶片被纺丝，同时将清洁流体施加到半导体晶片的顶表面以清除多余的光致抗蚀剂。施加冲洗溶液以冲洗半导体晶片中任何剩余的杂质。为了减少由于冲洗溶液干燥时由表面张力引起的光致抗蚀剂特征的应力，哪些应力可能导致特征的翻倒，半导体晶片在可密封的室内的蒸汽环境中被干燥。通过将惰性气体与气化表面张力调节流体结合而形成的蒸汽环境产生马兰戈尼效应以降低冲洗溶液的表面张力。任选地，为了进一步降低表面张力，可以将表面活性剂引入冲洗溶液中，并且可以调节密封室内部的温度和压力。

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