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81. 发明授权

US06838863B2 Voltage converter utilizing independently switched inductors 有权
标题翻译：采用独立开关电感的电压转换器
公开(公告)号：US06838863B2
公开(公告)日：2005-01-04
申请号：US10330555
申请日：2002-12-30
申请人： Peter Hazucha , Gerhard Schrom , Tanay Karnik , Volkan Kursun , Siva Narendra
发明人： Peter Hazucha , Gerhard Schrom , Tanay Karnik , Volkan Kursun , Siva Narendra
IPC分类号： H01F29/02 , H02M3/158 , H02M3/337 , G05F1/40 , G05F1/44
CPC分类号： H02M3/1584 , H01F29/02 , H02M3/337 , H02M2001/0074 , H02M2001/0077 , H02M2001/009
摘要： Embodiments of the present invention relate to independently switched inductors in a voltage converter. Each voltage transforming inductor of a voltage converter may be deignated a switch or bridge at each opposing terminal. The function of these switches is to periodically reverse the polarity of voltage across the inductors. By configuring independently switched inductors in series, the frustration of voltage tolerance limitations of the switches is mitigated.

82. 发明申请

US20070052446A1 DRIVER CIRCUIT 有权
标题翻译：驱动电路
公开(公告)号：US20070052446A1
公开(公告)日：2007-03-08
申请号：US11277117
申请日：2006-03-21
申请人： Gerhard Schrom , Peter Hazucha , Jae-Hong Hahn , Vivek De
发明人： Gerhard Schrom , Peter Hazucha , Jae-Hong Hahn , Vivek De
IPC分类号： H03K19/0175
CPC分类号： H03K17/691 , H03K19/0013
摘要： A circuit includes a first driver, a second driver, and a transformer coupled to the first and second driver. In operation, the first driver receives a first signal from a first input port, the second driver receives a time-delayed version of the first signal from a second input port, and the transformer provides provide an output signal to an output port. A method includes receiving a first input signal, receiving a second input signal, and then processing the first input signal and the second input signal. The second input signal is a time-delayed version of the first input signal and the processing of the first input signal and the second input signal generates a half-raised cosine signal.
摘要翻译：电路包括第一驱动器，第二驱动器和耦合到第一和第二驱动器的变压器。在操作中，第一驱动器从第一输入端口接收第一信号，第二驱动器从第二输入端口接收第一信号的时间延迟版本，并且变压器向输出端口提供输出信号。一种方法包括接收第一输入信号，接收第二输入信号，然后处理第一输入信号和第二输入信号。第二输入信号是第一输入信号的时间延迟版本，第一输入信号和第二输入信号的处理产生半升余弦信号。

83. 发明授权

US07199617B1 Level shifter 有权
标题翻译：电平移位器
公开(公告)号：US07199617B1
公开(公告)日：2007-04-03
申请号：US11111060
申请日：2005-04-21
申请人： Gerhard Schrom , Dinesh Somasekhar , Peter Hazucha , Stephen Tang , Vivek De
发明人： Gerhard Schrom , Dinesh Somasekhar , Peter Hazucha , Stephen Tang , Vivek De
IPC分类号： H04K19/094 , H04K19/0175
CPC分类号： H03K19/018528
摘要： A level shifting device comprises an input stage, a cascode stage, a cross-coupled stage, and an output stage. The input stage may receive a data signal or binary logic input in a first data range, a complement of the data signal, and a first voltage. The cascode stage may receive a first voltage and may be connected to the input stage. The cross-coupled stage may be adapted to isolate the first voltage and may be connected to the cascode stage. The output stage may receive a second voltage, provide an output, and be connected to the cross-coupled stage. The cascode stage may be adapted to provide the first voltage as the output when the logic input is a first value and provide the second voltage as the output when the logic input is a second value. Other embodiments are also claimed and described.
摘要翻译：电平移位装置包括输入级，共源共栅级，交叉耦合级和输出级。输入级可以在第一数据范围内接收数据信号或二进制逻辑输入，数据信号的补码和第一电压。共源共栅级可以接收第一电压并且可以连接到输入级。交叉耦合级可以适于隔离第一电压并且可以连接到共源共栅级。输出级可以接收第二电压，提供输出，并连接到交叉耦合级。当逻辑输入是第一值时，共源共栅级可以适于提供第一电压作为输出，并且当逻辑输入是第二值时提供第二电压作为输出。还要求保护和描述其它实施例。

84. 发明申请

US20050146356A1 Driver circuit 失效
标题翻译：驱动电路
公开(公告)号：US20050146356A1
公开(公告)日：2005-07-07
申请号：US10749928
申请日：2003-12-29
申请人： Gerhard Schrom , Peter Hazucha , Jae-Hong Hahn , Vivek De
发明人： Gerhard Schrom , Peter Hazucha , Jae-Hong Hahn , Vivek De
IPC分类号： H03K17/691 , H03K19/00 , H03K19/0175
CPC分类号： H03K17/691 , H03K19/0013
摘要： A circuit includes a first driver, a second driver, and a transformer coupled to the first and second driver. In operation, the first driver receives a first signal from a first input port, the second driver receives a time-delayed version of the first signal from a second input port, and the transformer provides provide an output signal to an output port. A method includes receiving a first input signal, receiving a second input signal, and then processing the first input signal and the second input signal. The second input signal is a time-delayed version of the first input signal and the processing of the first input signal and the second input signal generates a half-raised cosine signal.
摘要翻译：电路包括第一驱动器，第二驱动器和耦合到第一和第二驱动器的变压器。在操作中，第一驱动器从第一输入端口接收第一信号，第二驱动器从第二输入端口接收第一信号的时间延迟版本，并且变压器向输出端口提供输出信号。一种方法包括接收第一输入信号，接收第二输入信号，然后处理第一输入信号和第二输入信号。第二输入信号是第一输入信号的时间延迟版本，第一输入信号和第二输入信号的处理产生半升余弦信号。

85. 发明授权

US07265607B1 Voltage regulator 有权
标题翻译：电压调节器
公开(公告)号：US07265607B1
公开(公告)日：2007-09-04
申请号：US10930200
申请日：2004-08-31
申请人： Saravanan Rajapandian , Peter Hazucha , Tanay Karnik
发明人： Saravanan Rajapandian , Peter Hazucha , Tanay Karnik
IPC分类号： G05F1/10
CPC分类号： G05F1/56
摘要： A device comprises an active-pull-up stage and an active-pull-down stage. The device receives at least one reference voltage and provides an regulated output voltage to at least one load. The active-pull-up and active-pull-down stages are adapted to source or sink a current delivered to or received from the at least one load to regulate the output voltage provided to the at least one load. Other embodiments and methods are also claimed and described.
摘要翻译：一种装置包括有源上拉电平和有源下拉电平。该装置接收至少一个参考电压，并向至少一个负载提供稳定的输出电压。有源上拉和有源下拉级适于源或者传送传送到或从所述至少一个负载接收的电流以调节提供给所述至少一个负载的输出电压。还要求和描述其他实施例和方法。

86. 发明授权

US07212021B2 Manufacturing integrated circuits and testing on-die power supplies using distributed programmable digital current sinks 有权
标题翻译：使用分布式可编程数字电流源制造集成电路和片上电源测试
公开(公告)号：US07212021B2
公开(公告)日：2007-05-01
申请号：US10097136
申请日：2002-03-12
申请人： Tanay Karnik , Peter Hazucha
发明人： Tanay Karnik , Peter Hazucha
IPC分类号： G01R31/26
CPC分类号： G01R31/31721 , G01R31/2839
摘要： A method for designing and testing on-die power supply, power distribution, and noise suppression techniques for integrated circuits such as microprocessors is described. A network of time varying loads is distributed along the power supply grid to facilitate testing of new power supplies and grids and noise suppression techniques before design of the chip is completed. Several programmable current sinks are described for presenting loads according to a preferred test-waveform current. Transient, including droop detection, and static testing is easily performed using the described methods and circuitry.
摘要翻译：描述了一种用于集成电路（如微处理器）的片上电源，配电和噪声抑制技术的设计和测试方法。时变负载网络沿着电源网格分布，以便在芯片设计完成之前便于测试新的电源和网格以及噪声抑制技术。描述了几个可编程电流吸收器，用于根据优选的测试波形电流呈现负载。使用所描述的方法和电路容易地执行瞬态，包括下垂检测和静态测试。

87. 发明授权

US06617890B1 Measuring power supply stability 有权
标题翻译：测量电源稳定性
公开(公告)号：US06617890B1
公开(公告)日：2003-09-09
申请号：US10104393
申请日：2002-03-22
申请人： Tsung-Hao Chen , Peter Hazucha , Atila Alvandpour , Tanay Karnik , Chung-Ping Chen
发明人： Tsung-Hao Chen , Peter Hazucha , Atila Alvandpour , Tanay Karnik , Chung-Ping Chen
IPC分类号： H03K5153
CPC分类号： G01R19/16538 , G06F1/28 , H03K5/08 , H03K5/153
摘要： A system for measuring the stability of a power signal from a power supply includes a threshold violation detector. The threshold violation detector includes a comparator and an indicator. The comparator has a power signal input, a threshold signal input, and a comparison result output, and is configured to compare the power signal on the power signal input with a threshold on the threshold signal input to present a comparison result signal on the comparison result output. The indicator has a threshold violation output and a comparison input that receives the comparison result signal from the comparator. The indicator presents a threshold violation signal on the threshold violation output when the comparison result signal indicates that the power signal has violated the threshold.
摘要翻译：用于测量来自电源的功率信号的稳定性的系统包括阈值违规检测器。阈值违规检测器包括比较器和指示器。比较器具有功率信号输入，阈值信号输入和比较结果输出，并且被配置为将功率信号输入上的功率信号与阈值信号输入上的阈值进行比较，以在比较结果上呈现比较结果信号输出。指示器具有阈值违反输出和比较输入，其从比较器接收比较结果信号。当比较结果信号指示电源信号已经违反阈值时，指示器在阈值违反输出上呈现阈值违反信号。

88. 发明授权

US08710869B2 High-speed comparator with asymmetric frequency response 有权
标题翻译：具有不对称频率响应的高速比较器
公开(公告)号：US08710869B2
公开(公告)日：2014-04-29
申请号：US10422238
申请日：2003-04-23
申请人： Peter Hazucha , Tsung-Hao Chen , Tanay Karnik , Chung-Ping Chen
发明人： Peter Hazucha , Tsung-Hao Chen , Tanay Karnik , Chung-Ping Chen
IPC分类号： H03K5/22 , H03K5/24
CPC分类号： H03K5/2481 , H03F3/45183 , H03F2203/45544 , H03F2203/45646
摘要： A comparator to provide an output voltage indicative of comparing an input voltage with a reference voltage, where the comparator has an asymmetric frequency response. With an asymmetric frequency response, the bandwidth of the input voltage may be greater than the bandwidth of the reference voltage. A comparator includes a differential pair of transistors coupled to a current mirror and biased by a current source, where in one embodiment, a capacitor shunts the sources of the differential pair. In a second embodiment, a capacitor couples the input voltage port to the gates of the current mirror transistors. In a third embodiment, the comparator utilizes both capacitors of the first and second embodiments.
摘要翻译：比较器，用于提供指示将输入电压与参考电压进行比较的输出电压，其中比较器具有不对称的频率响应。对于非对称频率响应，输入电压的带宽可能大于参考电压的带宽。比较器包括耦合到电流镜并由电流源偏置的晶体管的差分对，其中在一个实施例中，电容器分流差分对的源极。在第二实施例中，电容器将输入电压端口耦合到电流镜晶体管的栅极。在第三实施例中，比较器利用了第一和第二实施例的两个电容器。

89. 发明授权

US07042274B2 Regulated sleep transistor apparatus, method, and system 失效
标题翻译：调节型睡眠晶体管装置，方法和系统
公开(公告)号：US07042274B2
公开(公告)日：2006-05-09
申请号：US10673822
申请日：2003-09-29
申请人： Peter Hazucha , Tanay Karnik
发明人： Peter Hazucha , Tanay Karnik
IPC分类号： G05F1/40 , G05F1/44 , G05F1/56
CPC分类号： G05F1/46
摘要： A transistor may operate as a sleep transistor or as a regulator.
摘要翻译：晶体管可以作为睡眠晶体管或调节器工作。

90. 发明授权

US07038515B2 Soft-error rate hardened pulsed latch 失效
标题翻译：软错误率硬化脉冲锁存器
公开(公告)号：US07038515B2
公开(公告)日：2006-05-02
申请号：US10741560
申请日：2003-12-19
申请人： Stefan Rusu , Peter Hazucha , Tanay Karnik
发明人： Stefan Rusu , Peter Hazucha , Tanay Karnik
IPC分类号： H03K3/356
CPC分类号： H03K3/0375
摘要： A latch includes a memory unit, a transfer unit, an inversion unit, and an output unit. The Memory unit includes a number of storage nodes. The transfer unit transfers a data from a data input node to the storage nodes via a plurality of data paths. Each of the data paths includes a pass element controlled by a pulse. The inversion unit inverts the data before the data is transferred from the data input node to at least one of the storage nodes. The output unit outputs the data from the memory unit to a latch output node. The memory unit, the transfer unit, the inversion unit, and the output unit of the latch form a soft-error rate hardened latch structure with a reduced number of elements and reduced power consumption.
摘要翻译：锁存器包括存储器单元，转移单元，反转单元和输出单元。存储器单元包括多个存储节点。传送单元经由多个数据路径将数据从数据输入节点传送到存储节点。每个数据路径包括由脉冲控制的传递元件。在将数据从数据输入节点传送到至少一个存储节点之前，反转单元将数据反转。输出单元将数据从存储器单元输出到锁存输出节点。存储器单元，转移单元，反转单元和锁存器的输出单元形成具有减少元件数量并降低功耗的软错误率硬化锁存结构。

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