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    • 87. 发明申请
    • Various methods and apparatuses for an executable parameterized timing model
    • 用于可执行参数化定时模型的各种方法和装置
    • US20070083830A1
    • 2007-04-12
    • US11246809
    • 2005-10-07
    • Stephen HamiltonIan SwarbrickScott EvansWolf-Dietrich WeberJay Tomlinson
    • Stephen HamiltonIan SwarbrickScott EvansWolf-Dietrich WeberJay Tomlinson
    • G06F17/50G06F9/45
    • G06F17/5045G06F2217/78G06F2217/84
    • Methods and apparatuses are described for an Intellectual Property (IP) Generator for estimating timing, area and power constraints in an electronic design system. The IP Generator receives a user-supplied file having data describing a configuration of an intellectual property (IP) design, the data includes one or more configuration parameters. The IP Generator further enables a transformation of the user-supplied file into a register transfer level design description. Next, the IP Generator receives user-supplied technology parameters and data-flow information. The technology parameters describe a configuration of the IP design. Next, the IP Generator executes a timing module based on the configuration of the IP design as well as executes a timing model for each hierarchical level in the IP design. The timing model predicts timing paths of a final logic circuit. Further, a result of the timing model is provided to the user prior to enabling a transformation of a register transfer level design into the simulation of a gate-level circuit design. Lastly, after the timing model has been executed, is the enablement of the transformation of the register transfer level design into the simulation of the gate-level circuit design.
    • 描述了用于估计电子设计系统中的时间,面积和功率约束的知识产权(IP)发生器的方法和装置。 IP生成器接收具有描述知识产权(IP)设计的配置的数据的用户提供的文件,该数据包括一个或多个配置参数。 IP生成器还可以将用户提供的文件转换为注册传输级设计描述。 接下来,IP生成器接收用户提供的技术参数和数据流信息。 技术参数描述了IP设计的配置。 接下来,IP生成器基于IP设计的配置执行定时模块,并且为IP设计中的每个层级执行定时模型。 定时模型预测最终逻辑电路的定时路径。 此外,在将寄存器传送级别设计转换为门级电路设计的仿真之前,将定时模型的结果提供给用户。 最后,在执行定时模型之后,将寄存器传输级设计的转换实现为门级电路设计的仿真。