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    • 82. 发明申请
    • SPACE DIVERSITY METHOD
    • 空间多样性方法
    • US20110268038A1
    • 2011-11-03
    • US13143661
    • 2009-06-30
    • Jing JiangYunfeng SunKaibo Tian
    • Jing JiangYunfeng SunKaibo Tian
    • H04W4/00
    • H04B7/0671H04B7/068
    • A space diversity method is disclosed having the steps of: setting space-frequency block coder (SFBC) based on Alamouti coder as the minimum unit of space-time coder; orthogonally processing the SFBC to acquire the transmission signals of part of antenna ports in eight antenna ports, and cyclically delaying the acquired transmission signals of antenna ports to obtain the transmission signals of the rest antenna ports; transmitting the acquired transmission signal in the corresponding time and sub-carrier by each antenna port. A space diversity device is also provided which has an orthogonal processing module, a signal cyclic delay module and a transmitting module. With the method and device, the eight-antenna data transmission in the long time evolution (LTE) advanced system is achieved, and better diversity gain is acquired without adding extra pilot overhead.
    • 公开了一种空间分集方法,具有以下步骤:将基于Alamouti编码器的空间频率块编码器(SFBC)设置为空时编码器的最小单位; 正交处理SFBC以获取八个天线端口中部分天线端口的发送信号,并且循环地延迟所获取的天线端口的发送信号,以获得其余天线端口的发送信号; 通过每个天线端口在相应的时间和子载波中发送所获取的传输信号。 还提供了具有正交处理模块,信号循环延迟模块和发送模块的空间分集装置。 通过该方法和装置,实现了长时间演进(LTE)高级系统中的八天线数据传输,并且在不增加额外的导频开销的情况下获得更好的分集增益。
    • 85. 发明申请
    • Restricted Cyclic Shift Configuration for Random Access Preambles in Wireless Networks
    • 无线网络随机接入前导限制循环移位配置
    • US20090073944A1
    • 2009-03-19
    • US12209403
    • 2008-09-12
    • Jing JiangPierre BertrandTarik Muharemovic
    • Jing JiangPierre BertrandTarik Muharemovic
    • H04W8/00
    • H04J13/0062H04J11/00H04J13/22H04L5/0007
    • Transmission of random access preamble structures within a cellular wireless network is based on the use of cyclic shifted constant amplitude zero autocorrelation (“CAZAC”) sequences to generate the random access preamble signal. A pre-defined set of sequences is arranged in a specific order. Within the predefined set of sequences is an ordered group of sequences that is a proper subset of the pre-defined set of sequences. Within a given cell, up to 64 sequences may need to be signaled. In order to minimize the associated overhead due to signaling multiple sequences, only one logical index is transmitted by a base station serving the cell and a user equipment within the cell derives the subsequent indexes according to the pre-defined ordering. Each sequence has a unique logical index. The ordering of sequences is identified by the logical indexes of the sequences, with each logical index uniquely mapped to a generating index. When a UE needs to transmit, it produces a second sequence using the received indication of the logical index of the first sequence and an auxiliary value and then produces a transmission signal by modulating the second sequence. The auxiliary value is selected from one of two sets based on a set indicator broadcast by the eNB
    • 蜂窝无线网络内的随机接入前同步码结构的传输是基于使用循环移位恒幅零自相关(“CAZAC”)序列来生成随机接入前同步信号的。 按照特定顺序排列预定义的序列集合。 在预定义的序列集合内,是序列的有序组,其是预定义序列集合的适当子集。 在给定的小区内,可能需要发信号通知多达64个序列。 为了最小化由于信令多个序列引起的相关开销,仅由服务于小区的基站发送一个逻辑索引,并且小区内的用户设备根据预定义的顺序导出后续索引。 每个序列都有唯一的逻辑索引。 序列的顺序由序列的逻辑索引识别,每个逻辑索引唯一映射到生成索引。 当UE需要发送时,其使用接收到的第一序列的逻辑索引的指示和辅助值产生第二序列,然后通过调制第二序列来产生传输信号。 基于由eNB广播的设定指示符,从两组中选择一个辅助值
    • 88. 发明申请
    • METHOD AND APPARATUS FOR RATELESS SOURCE CODING WITH/WITHOUT DECODER SIDE INFORMATION
    • 用于具有/不具有解码器侧信息的无源源编码的方法和装置
    • US20080320363A1
    • 2008-12-25
    • US11764876
    • 2007-06-19
    • Dake HeAshish JagmohanJing Jiang
    • Dake HeAshish JagmohanJing Jiang
    • G06F11/10
    • H03M13/1102H03M7/30H03M13/6312H03M13/6362
    • A method of and system for rateless source coding are disclosed. The method comprises the steps of providing a set of low-density parity check (LDPC) codes, each of which accepts a range of data input lengths and a range of target compression rates; identifying a data input having a data input length; and identifying a desired compression rate. The method comprises the further steps of selecting one of said LDPC codes based on said data input length and desired compression rate; encoding the data input, using the selected LDPC code, to generate a sequence of data values; and puncturing some of said encoded data values to achieve the desired compression rate. Preferably, the encoding step includes the steps of generating a syndrome and a parity sequence from the data input, puncturing the generated parity sequence, and mixing a remaining portion of the data input with the punctuated parity sequence.
    • 公开了一种用于无源源编码的方法和系统。 该方法包括以下步骤:提供一组低密度奇偶校验(LDPC)码,每一个码接受数据输入长度的范围和目标压缩率的范围; 识别具有数据输入长度的数据输入; 并识别期望的压缩率。 该方法包括以下步骤:基于所述数据输入长度和期望的压缩率来选择所述LDPC码之一; 使用所选择的LDPC码对数据输入进行编码,以生成数据值序列; 以及对某些所述编码的数据值进行穿孔以实现所需的压缩率。 优选地,编码步骤包括以下步骤:从数据输入产生校正子和奇偶校验序列,对所生成的奇偶校验序列进行穿孔,以及将输入的数据的剩余部分与标点奇偶校验序列进行混合。
    • 90. 发明授权
    • Mixed mode verifier
    • 混合模式验证器
    • US07360187B2
    • 2008-04-15
    • US11242599
    • 2005-09-30
    • Kevin D. JonesThomas J. ShefflerKathryn M. MossawirQiang HongPaul WongJing Jiang
    • Kevin D. JonesThomas J. ShefflerKathryn M. MossawirQiang HongPaul WongJing Jiang
    • G06F17/50
    • G06F17/504
    • A method and system for formally verifying designs having elements from more than a single design domain is described. An example system allows formal verification of a design containing mixed analog and digital subparts. The system may use different proof engines to solve an appropriate sub-partition of the entire design, and may provide a framework for translating between the different domains to create a unified result. For example, a digital proof engine may be used for a digital only subpart, while an analog proof engine may be used for an analog only subpart. The system may use the partitioning results to determine translators between the various domains, and an order in which the proof engines are applied.
    • 描述了用于正式验证来自多于单个设计域的元件的设计的方法和系统。 示例系统允许对包含混合模拟和数字子部件的设计进行形式验证。 系统可以使用不同的证明引擎来解决整个设计的适当子分区,并且可以提供用于在不同域之间进行翻译以创建统一结果的框架。 例如,数字证明引擎可以用于仅数字的子部件,而模拟证明引擎可以用于仅模拟子部件。 系统可以使用分区结果来确定各个域之间的翻译器以及应用证明引擎的顺序。