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81. 发明授权

US08248422B2 Efficient texture processing of pixel groups with SIMD execution unit 有权
标题翻译：具有SIMD执行单元的像素组的高效纹理处理
公开(公告)号：US08248422B2
公开(公告)日：2012-08-21
申请号：US12016306
申请日：2008-01-18
申请人： Eric Oliver Mejdrich , Paul Emery Schardt , Robert Allen Shearer
发明人： Eric Oliver Mejdrich , Paul Emery Schardt , Robert Allen Shearer
IPC分类号： G06F15/80 , G09G5/37 , G09G5/00
CPC分类号： G06F9/30036 , G06F9/3851 , G06F9/3887 , G06T1/20 , G06T15/04
摘要： A circuit arrangement and method perform concurrent texture processing of groups of pixels with a single instruction multiple data (SIMD) execution unit to improve the utilization of the SIMD execution unit when performing scalar operations associated with a texture processing algorithm. In addition, when utilized in connection with a multi-threaded SIMD execution unit, groups of pixels may be concurrently processed in different threads executed by the SIMD execution unit to further maximize the utilization of the SIMD execution unit by reducing the adverse effects of dependencies in scalar and/or vector operations incorporated into a texture processing algorithm.
摘要翻译：电路布置和方法利用单指令多数据（SIMD）执行单元执行像素组的并行纹理处理，以在执行与纹理处理算法相关联的标量运算时提高SIMD执行单元的利用率。此外，当与多线程SIMD执行单元结合使用时，可以在由SIMD执行单元执行的不同线程中同时处理像素组，以通过减少SIMD执行单元的依赖性的不利影响来进一步最大化利用SIMD执行单元结合到纹理处理算法中的标量和/或矢量操作。

82. 发明授权

US08085267B2 Stochastic addition of rays in a ray tracing image processing system 有权
标题翻译：在光线跟踪图像处理系统中随机添加光线
公开(公告)号：US08085267B2
公开(公告)日：2011-12-27
申请号：US11668522
申请日：2007-01-30
申请人： Jeffrey Douglas Brown , Russell Dean Hoover , Eric Oliver Mejdrich
发明人： Jeffrey Douglas Brown , Russell Dean Hoover , Eric Oliver Mejdrich
IPC分类号： G06T15/50
CPC分类号： G06T15/06 , G06T15/40
摘要： According to embodiments of the invention, rays may be stochastically culled before they are issued into the three-dimensional scene. Stochastically culling rays may reduce the number of rays which need to be traced by the image processing system. Furthermore, by stochastically culling rays before they are issued into the three-dimensional scene, minor imperfections may be added to the final rendered image, thereby improving the realism of the rendered image. Therefore, stochastic culling of rays may improve the performance of the image processing system by reducing workload imposed on the image processing system and improving the realism of the images rendered by the image processing system. According to another embodiment of the invention, the realism of images rendered by the image processing system may also be improved by stochastically adding secondary rays after ray-primitive intersections have occurred.
摘要翻译：根据本发明的实施例，射线可以在它们被发放到三维场景之前被随机地淘汰。随机剔除光线可能减少图像处理系统需要追踪的光线数量。此外，通过在将它们发布到三维场景之前随机剔除光线，可以将最小的缺陷添加到最终渲染图像，从而改善渲染图像的真实性。因此，通过减少图像处理系统的工作量，提高图像处理系统所呈现的图像的真实性，可以提高图像处理系统的性能。根据本发明的另一个实施例，图像处理系统呈现的图像的真实性也可以通过在发生光线原始交点之后随机添加二次光线来改善。

83. 发明授权

US07996621B2 Data cache invalidate with data dependent expiration using a step value 有权
标题翻译：数据缓存无效，数据相关到期使用步进值
公开(公告)号：US07996621B2
公开(公告)日：2011-08-09
申请号：US11776731
申请日：2007-07-12
申请人： Jeffrey Douglas Brown , Russell Dean Hoover , Eric Oliver Mejdrich , Kenneth Michael Valk
发明人： Jeffrey Douglas Brown , Russell Dean Hoover , Eric Oliver Mejdrich , Kenneth Michael Valk
IPC分类号： G06F12/12
CPC分类号： G06F12/0895 , Y02D10/13
摘要： According to embodiments of the invention, a step value and a step-interval cache coherency protocol may be used to update and invalidate data stored within cache memory. A step value may be an integer value and may be stored within a cache directory entry associated with data in the memory cache. Upon reception of a cache read request, along with the normal address comparison to determine if the data is located within the cache a current step value may be compared with the stored step value to determine if the data is current. If the step values match, the data may be current and a cache hit may occur. However, if the step values do not match, the requested data may be provided from another source. Furthermore, an application may update the current step value to invalidate old data stored within the cache and associated with a different step value.
摘要翻译：根据本发明的实施例，可以使用步长值和步进间隔高速缓存一致性协议来更新和使存储在高速缓冲存储器中的数据无效。步数值可以是整数值，并且可以存储在与存储器高速缓存中的数据相关联的高速缓存目录条目中。在接收到缓存读取请求时，连同正常地址比较以确定数据是否位于高速缓存内，可以将当前步长值与存储的步长值进行比较，以确定数据是否为当前值。如果步数值匹配，数据可能是当前的，并且可能会发生高速缓存命中。然而，如果步骤值不匹配，则可以从另一个源提供所请求的数据。此外，应用程序可以更新当前步骤值以使存储在高速缓存中并与不同步长值相关联的旧数据无效。

84. 发明授权

US07973804B2 Image processing with highly threaded texture fragment generation 有权
标题翻译：具有高度线程纹理片段生成的图像处理
公开(公告)号：US07973804B2
公开(公告)日：2011-07-05
申请号：US12045737
申请日：2008-03-11
申请人： Eric Oliver Mejdrich , Paul Emery Schardt , Robert Allen Shearer
发明人： Eric Oliver Mejdrich , Paul Emery Schardt , Robert Allen Shearer
IPC分类号： G06F15/16 , G06F15/80 , G06F15/00 , G06T1/00 , G09G5/00 , G06K9/60 , H04L12/28
CPC分类号： G06T15/005
摘要： A circuit arrangement and method support a multithreaded rendering architecture capable of dynamically routing pixel fragments from a pixel fragment generator to any pixel shader from among a pool of pixel shaders. The pixel fragment generator is therefore not tied to a specific pixel shader, but is instead able to utilize multiple pixel shaders in a pool of pixel shaders to minimize bottlenecks and improve overall hardware utilization and performance during image processing.
摘要翻译：电路布置和方法支持能够将像素片段生成器中的像素片段从像素着色器池中的任何像素着色器动态路由的多线程渲染架构。因此，像素片段生成器不与特定的像素着色器相关联，而是能够在像素着色器池中使用多个像素着色器来最小化瓶颈并提高图像处理期间的整体硬件利用率和性能。

85. 发明申请

US20090231349A1 Rolling Context Data Structure for Maintaining State Data in a Multithreaded Image Processing Pipeline 有权
标题翻译：滚动上下文数据结构，用于维护多线程图像处理流水线中的状态数据
公开(公告)号：US20090231349A1
公开(公告)日：2009-09-17
申请号：US12046573
申请日：2008-03-12
申请人： Eric Oliver Mejdrich , Paul Emery Schardt , Robert Allen Shearer
发明人： Eric Oliver Mejdrich , Paul Emery Schardt , Robert Allen Shearer
IPC分类号： G06T1/20
CPC分类号： G06T15/005
摘要： A multithreaded rendering software pipeline architecture utilizes a rolling context data structure to store multiple contexts that are associated with different image elements that are being processed in the software pipeline. Each context stores state data for a particular image element, and the association of each image element with a context is maintained as the image element is passed from stage to stage of the software pipeline, thus ensuring that the state used by the different stages of the software pipeline when processing the image element remains coherent irrespective of state changes made for other image elements being processed by the software pipeline. Multiple image elements may therefore be processed concurrently by the software pipeline, and often without regard for synchronization or serialization of state changes that affect only certain image elements.
摘要翻译：多线程渲染软件流水线架构利用滚动上下文数据结构来存储与在软件流水线中处理的不同图像元素相关联的多个上下文。每个上下文存储特定图像元素的状态数据，并且当图像元素从软件流水线的阶段传递到阶段时，维护每个图像元素与上下文的关联，从而确保由图像元素的不同阶段使用的状态处理图像元素时的软件流水线保持一致，而与由软件流水线处理的其他图像元素的状态变化无关。因此，多个图像元素可以由软件管线同时处理，并且通常不考虑仅影响某些图像元素的状态改变的同步或串行化。

86. 发明申请

US20090179902A1 Dynamic Data Type Aligned Cache Optimized for Misaligned Packed Structures 有权
标题翻译：动态数据类型对齐缓存针对未对齐的打包结构进行了优化
公开(公告)号：US20090179902A1
公开(公告)日：2009-07-16
申请号：US12013780
申请日：2008-01-14
申请人： Miguel Comparan , Russell Dean Hoover , Eric Oliver Mejdrich
发明人： Miguel Comparan , Russell Dean Hoover , Eric Oliver Mejdrich
IPC分类号： G06F15/16 , G06F13/00
CPC分类号： G06F12/0862 , G06F12/0886
摘要： A method and apparatus for processing vector data is provided. A processing core may have a data cache and a relatively smaller vector data cache. The vector data cache may be optimally sized to store vector data structures that are smaller than full data cache lines.
摘要翻译：提供了一种用于处理向量数据的方法和装置。处理核心可以具有数据高速缓存和相对较小的向量数据高速缓存。矢量数据高速缓存可以被最优化地大小以存储小于全数据高速缓存行的向量数据结构。

87. 发明申请

US20090150648A1 Vector Permute and Vector Register File Write Mask Instruction Variant State Extension for RISC Length Vector Instructions 审中-公开
标题翻译：向量权限和矢量寄存器文件写掩码指令用于RISC长度向量指令的变量状态扩展
公开(公告)号：US20090150648A1
公开(公告)日：2009-06-11
申请号：US11951416
申请日：2007-12-06
申请人： Eric Oliver Mejdrich
发明人： Eric Oliver Mejdrich
IPC分类号： G06F15/76 , G06F9/30
CPC分类号： G06F9/30032 , G06F9/30014 , G06F9/30036 , G06F9/3885 , G06T15/06 , G06T2200/28
摘要： Embodiments of the invention generally relate to the field of image processing, and more specifically to instructions and hardware for supporting image processing. An integrated processing unit configured to process vector instructions and vector permute instructions is provided. A vector permute instruction may be issued to the integrated processing unit to set controls of one or more multiplexers so that the multiplexers rearrange the results of a subsequent vector instruction.
摘要翻译：本发明的实施例一般涉及图像处理领域，更具体地涉及用于支持图像处理的指令和硬件。提供了一种被配置为处理向量指令和向量置换指令的集成处理单元。可以向集成处理单元发出矢量置换指令以设置一个或多个复用器的控制，使得多路复用器重新排列随后的矢量指令的结果。

88. 发明授权

US07469312B2 Computer system bus bridge 失效
标题翻译：计算机系统总线桥
公开(公告)号：US07469312B2
公开(公告)日：2008-12-23
申请号：US11064568
申请日：2005-02-24
申请人： Giora Biran , Robert Allen Drehmel , Robert Spencer Horton , Mark E. Kautzman , Jamie Randall Kuesel , Ming-i Mark Lin , Eric Oliver Mejdrich , Clarence Rosser Ogilvie , Charles S. Woodruff
发明人： Giora Biran , Robert Allen Drehmel , Robert Spencer Horton , Mark E. Kautzman , Jamie Randall Kuesel , Ming-i Mark Lin , Eric Oliver Mejdrich , Clarence Rosser Ogilvie , Charles S. Woodruff
IPC分类号： G06F13/36 , G06F3/00
CPC分类号： G06F13/4059 , G06F12/0831
摘要： A method for bridging between a high speed computer processor bus and a high speed output bus. The preferred embodiment is a method for bridging between a GPUL bus for a GPUL PowerPC microprocessor from International Business Machines Corporation (IBM) and an output high speed interface (MPI).
摘要翻译：一种用于在高速计算机处理器总线和高速输出总线之间桥接的方法。优选实施例是用于桥接国际商业机器公司（IBM）的GPUL PowerPC微处理器的GPUL总线和输出高速接口（MPI）之间的桥接方法。

89. 发明申请

US20080238920A1 Color Buffer Contrast Threshold for Adaptive Anti-Aliasing 有权
标题翻译：自适应抗锯齿的色彩缓冲区对比阈值
公开(公告)号：US20080238920A1
公开(公告)日：2008-10-02
申请号：US11693221
申请日：2007-03-29
申请人： Jeffrey Douglas Brown , Russell Dean Hoover , Eric Oliver Mejdrich
发明人： Jeffrey Douglas Brown , Russell Dean Hoover , Eric Oliver Mejdrich
IPC分类号： G06T15/50
CPC分类号： G06T15/06
摘要： According to one embodiment of the invention, by increasing the number of rays issued through adjacent pixels with colors of high contrast while maintaining the number of rays issued through adjacent pixels which do not have colors of high contrast, a ray tracing image processing system may render an anti-aliased image while minimizing the increase in workload experienced by the image processing system. Additionally, according to another embodiment of the invention, by maintaining the number of rays issued through adjacent pixels which have colors of low contrast while increasing the number of rays issued through adjacent pixels which do not have colors of low contrast, the image processing system may reduce workload experienced while performing ray tracing while maintaining the quality of the rendered image.
摘要翻译：根据本发明的一个实施例，通过在保持通过不具有高对比度的颜色的相邻像素发出的光线的数量的同时增加通过相邻像素发出的具有高对比度的颜色的光线的数量，光线跟踪图像处理系统可以呈现抗锯齿图像，同时最小化图像处理系统经历的工作量的增加。此外，根据本发明的另一实施例，通过保持通过具有低对比度的颜色的相邻像素发出的光线的数量，同时增加通过不具有低对比度的颜色的相邻像素发出的光线的数量，图像处理系统减少在执行光线跟踪同时保持渲染图像的质量时遇到的工作量。

90. 发明申请

US20080114942A1 Dynamic Data Cache Invalidate with Data Dependent Expiration 有权
标题翻译：动态数据缓存无效，数据依赖到期
公开(公告)号：US20080114942A1
公开(公告)日：2008-05-15
申请号：US11559090
申请日：2006-11-13
申请人： Jeffrey Douglas Brown , Russell Dean Hoover , Eric Oliver Mejdrich
发明人： Jeffrey Douglas Brown , Russell Dean Hoover , Eric Oliver Mejdrich
IPC分类号： G06F12/08
CPC分类号： G06F12/0875 , G06F12/0808 , G06F12/1045 , G06T1/60
摘要： According to embodiments of the invention, a distributed time base signal may be coupled to a memory directory which provides address translation for data located within a memory cache. The memory directory may have attribute bits which indicate whether or not the memory entries have been accessed by the distributed time base signal. Furthermore, the memory directory may have attribute bits which indicate whether or not a memory directory entry should be considered invalid after an access to the memory entry by the distributed time base signal. If the memory directory entry has been accessed by the distributed time base signal and the memory directory entry should be considered invalid after the access by the time base signal, any attempted address translation using the memory directory entry may cause a cache miss. The cache miss may initiate the retrieval of valid data from memory.
摘要翻译：根据本发明的实施例，分布式时基信号可以耦合到为位于存储器高速缓存内的数据提供地址转换的存储器目录。存储器目录可以具有指示存储器条目是否已经被分布式时基信号访问的属性位。此外，存储器目录可以具有指示在通过分布式时基信号访问存储器条目之后存储目录条目是否应被视为无效的属性位。如果通过分布式时基信号访问存储器目录条目，并且在通过时基信号访问之后，存储器目录条目应被视为无效，则使用存储器目录条目的任何尝试的地址转换可能导致高速缓存未命中。高速缓存未命中可以启动从存储器检索有效数据。

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