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81. 发明授权

US08855993B2 Integrated circuit design simulation matrix interpolation 有权
标题翻译：集成电路设计仿真矩阵插值
公开(公告)号：US08855993B2
公开(公告)日：2014-10-07
申请号：US13251517
申请日：2011-10-03
申请人： Peter A. Habitz , Amol A. Joshi
发明人： Peter A. Habitz , Amol A. Joshi
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Methods and systems perform a simulation on an integrated circuit design by applying a first value to a first variable and a second value to a second variable of the simulation to produce a first matrix corner simulation value. The methods and systems repeat the simulation using different values for the first and said second variables to produce a second matrix corner simulation value, a third matrix corner simulation value, and a fourth matrix corner simulation value. The methods and systems create a matrix, and the matrix has the first matrix corner simulation value, the second matrix corner simulation value, the third matrix corner simulation value, and the fourth matrix corner simulation value. The methods and systems interpolate all remaining values within the matrix based upon existing simulation values within the matrix.
摘要翻译：方法和系统通过将第一值应用于第一变量和第二值到模拟的第二变量来对集成电路设计进行仿真以产生第一矩阵角模拟值。方法和系统使用不同的值对第一和第二变量重复模拟，以产生第二矩阵角模拟值，第三矩阵角模拟值和第四矩阵角模拟值。方法和系统创建矩阵，矩阵具有第一矩阵角模拟值，第二矩阵角模拟值，第三矩阵角模拟值和第四矩阵角模拟值。方法和系统基于矩阵内的现有模拟值来内插矩阵内的所有剩余值。

82. 发明授权

US08543966B2 Test path selection and test program generation for performance testing integrated circuit chips 有权
标题翻译：测试路径选择和测试程序生成用于性能测试集成电路芯片
公开(公告)号：US08543966B2
公开(公告)日：2013-09-24
申请号：US13294210
申请日：2011-11-11
申请人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Jinjun Xiong
发明人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Jinjun Xiong
IPC分类号： G06F11/22 , G06F17/50
CPC分类号： G01R31/31726 , G01R31/318541
摘要： A method of test path selection and test program generation for performance testing integrated circuits. The method includes identifying clock domains having multiple data paths of an integrated circuit design having multiple clock domains; selecting, from the data paths, critical paths for each clock domain of the multiple clock domains; using a computer, for each clock domain of the multiple clock domain, selecting the sensitizable paths of the critical paths; for each clock domain of the multiple clock domain, selecting test paths from the sensitizable critical paths; and using a computer, creating a test program to performance test the test paths.
摘要翻译：一种用于性能测试集成电路的测试路径选择和测试程序生成的方法。该方法包括识别具有具有多个时钟域的集成电路设计的多个数据路径的时钟域; 从数据路径中选择多个时钟域的每个时钟域的关键路径; 使用计算机，对于多个时钟域的每个时钟域，选择关键路径的可敏化路径; 对于多个时钟域的每个时钟域，从敏感关键路径中选择测试路径; 并使用计算机，创建测试程序来测试测试路径。

83. 发明申请

US20130226536A1 DYNAMICALLY DETERMINING NUMBER OF SIMULATIONS REQUIRED FOR CHARACTERIZING INTRA-CIRCUIT INCONGRUENT VARIATIONS 有权
标题翻译：动态确定表征电路内容变化所需的模拟数量
公开(公告)号：US20130226536A1
公开(公告)日：2013-08-29
申请号：US13406897
申请日：2012-02-28
申请人： Peter A. Habitz , Amol A. Joshi , Amith Singhee , James E. Sundquist , Wangyang Zhang
发明人： Peter A. Habitz , Amol A. Joshi , Amith Singhee , James E. Sundquist , Wangyang Zhang
IPC分类号： G06F17/50 , G06F17/10
CPC分类号： G06F17/5036 , G06F17/50 , G06F17/5031 , G06F2217/10 , G06F2217/84
摘要： A method is disclosed comprising using a circuit recognition engine running on a computerized device to detect a number and type devices in an integrated circuit. The method characterizes device variation by selecting a set of dominant active devices and performing simulation using the set of dominant active devices. Three different options may be used to optimize the number of simulations for any arc/slew/load combination. Aggressive reduction uses a minimal number of simulations at the cost of some accuracy loss, conservative reduction reduces the number of simulations with negligible accuracy loss, and dynamic reduction dynamically determines the minimum number of simulations needed for a given accuracy requirement.
摘要翻译：公开了一种方法，其包括使用在计算机化设备上运行的电路识别引擎来检测集成电路中的数量和类型设备。该方法通过选择一组主导有源器件并使用该主导有源器件集来执行仿真来表征器件变化。可以使用三种不同的选项来优化任何电弧/压摆/负载组合的模拟次数。积极减少使用最少数量的模拟，以牺牲一些精度损失为代价，保守的减少可以减少精确度损失可忽略的模拟次数，动态减少动态地确定给定精度要求所需的最小模拟次数。

84. 发明授权

US08490040B2 Disposition of integrated circuits using performance sort ring oscillator and performance path testing 有权
标题翻译：使用性能分类环形振荡器和性能路径测试对集成电路进行处理
公开(公告)号：US08490040B2
公开(公告)日：2013-07-16
申请号：US13294220
申请日：2011-11-11
申请人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Jinjun Xiong
发明人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Jinjun Xiong
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G01R31/3016 , G01R31/31725
摘要： A method and system for dispositioning integrated circuit chips. The method includes performing a performance path test on an integrated circuit chip having one or more clock domains, the performance path test based on applying test patterns to selected sensitizable data paths of the integrated circuit chip at different clock frequencies; and dispositioning the integrated circuit chip based on results of the performance path test.
摘要翻译：一种配置集成电路芯片的方法和系统。该方法包括对具有一个或多个时钟域的集成电路芯片执行性能路径测试，该性能路径测试基于将测试图案应用于集成电路芯片的不同时钟频率的选择的可敏化数据路径; 并且基于性能路径测试的结果来布置集成电路芯片。

85. 发明申请

US20130125073A1 TEST PATH SELECTION AND TEST PROGRAM GENERATION FOR PERFORMANCE TESTING INTEGRATED CIRCUIT CHIPS 有权
标题翻译：性能测试集成电路卡的测试路径选择和测试程序生成
公开(公告)号：US20130125073A1
公开(公告)日：2013-05-16
申请号：US13294210
申请日：2011-11-11
申请人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Jinjun Xiong
发明人： Jeanne P. Bickford , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Jinjun Xiong
IPC分类号： G06F17/50
CPC分类号： G01R31/31726 , G01R31/318541
摘要： A method of test path selection and test program generation for performance testing integrated circuits. The method includes identifying clock domains having multiple data paths of an integrated circuit design having multiple clock domains; selecting, from the data paths, critical paths for each clock domain of the multiple clock domains; using a computer, for each clock domain of the multiple clock domain, selecting the sensitizable paths of the critical paths; for each clock domain of the multiple clock domain, selecting test paths from the sensitizable critical paths; and using a computer, creating a test program to performance test the test paths
摘要翻译：一种用于性能测试集成电路的测试路径选择和测试程序生成的方法。该方法包括识别具有具有多个时钟域的集成电路设计的多个数据路径的时钟域; 从数据路径中选择多个时钟域的每个时钟域的关键路径; 使用计算机，对于多个时钟域的每个时钟域，选择关键路径的可敏化路径; 对于多个时钟域的每个时钟域，从敏感关键路径中选择测试路径; 并使用计算机，创建测试程序来测试测试路径

86. 发明授权

US07823115B2 Method of generating wiring routes with matching delay in the presence of process variation 有权
标题翻译：在存在过程变化的情况下生成具有匹配延迟的布线路线的方法
公开(公告)号：US07823115B2
公开(公告)日：2010-10-26
申请号：US12108629
申请日：2008-04-24
申请人： Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Anthony D. Polson
发明人： Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a first wiring path, a second wiring path, etc. Two or more of the wiring paths are designed to have matching timing, such that the time needed for a signal to travel along the first wiring path is about the same time needed for a signal to travel along the second wiring path, the third path, etc. The method/service designs one or all of the wiring paths to make the paths traverse wire segments of about the same length and orientation, within each wiring level that the first wiring path and the second wiring path traverse. Also, this process makes the first wiring path and the second wiring path traverse the wire segments in the same order, within each wiring level that the first wiring path and the second wiring path traverse.
摘要翻译：电路设计中的平衡延迟的方法和服务从通过布线设计连接在一起的节点开始，或通过提供要被改变的初始布线设计。布线设计将具有许多布线路径，例如第一布线路径，第二布线路径等。两条或多条布线路径被设计成具有匹配的定时，使得信号沿着第一布线路径行进所需的时间信号沿着第二布线路径，第三路径等移动所需的大致相同的时间。该方法/服务设计一个或所有布线路径，以使路径穿过大约相同长度的线段，并且在第一布线路径和第二布线路径横越的各布线层内。此外，该处理使得第一布线路径和第二布线路径在第一布线路径和第二布线路径横越的各布线层内以相同的顺序横穿线段。

87. 发明申请

US20080201683A1 Method of Generating Wiring Routes with Matching Delay in the Presence of Process Variation 有权
公开(公告)号：US20080201683A1
公开(公告)日：2008-08-21
申请号：US12108629
申请日：2008-04-24
申请人： Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Anthony D. Polson
发明人： Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a first wiring path, a second wiring path, etc. Two or more of the wiring paths are designed to have matching timing, such that the time needed for a signal to travel along the first wiring path is about the same time needed for a signal to travel along the second wiring path, the third path, etc. The method/service designs one or all of the wiring paths to make the paths traverse wire segments of about the same length and orientation, within each wiring level that the first wiring path and the second wiring path traverse. Also, this process makes the first wiring path and the second wiring path traverse the wire segments in the same order, within each wiring level that the first wiring path and the second wiring path traverse.

88. 发明授权

US07266474B2 Ring oscillator structure and method of separating random and systematic tolerance values 失效
标题翻译：环形振荡器结构和分离随机和系统容差值的方法
公开(公告)号：US07266474B2
公开(公告)日：2007-09-04
申请号：US11162197
申请日：2005-08-31
申请人： Peter A. Habitz , Jerry D. Hayes
发明人： Peter A. Habitz , Jerry D. Hayes
IPC分类号： G06F11/30 , H03K3/03 , G01R23/00
CPC分类号： G05B23/0221 , G01R31/2648
摘要： A ring oscillator test structure comprises at least two overlapping rings that are switchable between different numbers of stages. A delay distribution is measured for various numbers of stages in a set of oscillators formed in different locations subject to different systematic delay effects. The delay distributions are analyzed to isolate the systematic and the random contributions to the standard deviation of the distributions.
摘要翻译：环形振荡器测试结构包括可在不同数量级之间切换的至少两个重叠环。测量在不同位置处形成的一组振荡器中的不同数量的级的延迟分布，其受到不同的系统延迟效应的影响。分析延迟分布，分析系统和随机贡献与分布的标准偏差。

89. 发明授权

US06477686B1 Method of calculating 3-dimensional fringe characteristics using specially formed extension shapes 失效
标题翻译：使用特殊形状的延伸形状计算3维条纹特征的方法
公开(公告)号：US06477686B1
公开(公告)日：2002-11-05
申请号：US09560577
申请日：2000-04-27
申请人： L. William Dewey, III , Peter A. Habitz
发明人： L. William Dewey, III , Peter A. Habitz
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： A structure and method for performing a capacitance extraction on an integrated circuit, includes determining a parallel-plate capacitance between devices on different levels within the integrated circuit, adding extension shapes around each of the devices, reducing an area of overlapping extension shapes, multiplying a remaining area of the extension shapes by a constant to produce a fringe capacitance; and summing the parallel-plate capacitance and the fringe capacitance.
摘要翻译：一种用于在集成电路上执行电容提取的结构和方法，包括：确定集成电路内不同级别的器件之间的平行板电容，在每个器件周围增加扩展形状，减少重叠扩展形状的面积，将延伸形状的剩余面积为常数以产生边缘电容; 并且平行板电容和边缘电容相加。

90. 发明授权

US06473887B1 Inclusion of global wires in capacitance extraction 失效
标题翻译：将全局线插入电容提取中
公开(公告)号：US06473887B1
公开(公告)日：2002-10-29
申请号：US09560065
申请日：2000-04-27
申请人： L. William Dewey, III , Peter A. Habitz , Edward W. Seibert
发明人： L. William Dewey, III , Peter A. Habitz , Edward W. Seibert
IPC分类号： G06F945
CPC分类号： G06F17/5036
摘要： A method and structure for performing capacitance extraction during the design of an integrated circuit includes inputting a specified wiring density and design requirements, determining a minimum spacing for wire segments based on the design requirements, calculating a transparency factor based on the wiring density, calculating a lateral capacitance assuming virtual wires are present in the integrated circuit, and calculating a vertical capacitance based on the transparency factor.
摘要翻译：在集成电路设计期间进行电容提取的方法和结构包括输入指定的布线密度和设计要求，根据设计要求确定线段的最小间距，根据布线密度计算透明度因子，计算出在集成电路中存在假想虚线的横向电容，并且基于透明度因子计算垂直电容。

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