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81. 发明授权

US07399686B2 Method and apparatus for making coplanar dielectrically-isolated regions of different semiconductor materials on a substrate 有权
标题翻译：用于在衬底上制造不同半导体材料的共面介电隔离区域的方法和装置
公开(公告)号：US07399686B2
公开(公告)日：2008-07-15
申请号：US11218198
申请日：2005-09-01
申请人： Howard Hao Chen , Louis Lu-Chen Hsu , Jack Allan Mandelman
发明人： Howard Hao Chen , Louis Lu-Chen Hsu , Jack Allan Mandelman
IPC分类号： H01L21/36 , H01L21/20
CPC分类号： H01L21/76254 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L27/1207
摘要： A semiconductor processing method includes providing a substrate, forming a plurality of semiconductor layers in the substrate, each of the semiconductor layers being distinct and selected from different groups of semiconductor element types, the semiconductor layers comprising first, second, and third semiconductor layers. The method further includes forming a nitride cap layer on the second semiconductor layer prior to forming the third semiconductor layer. Semiconductor structure formed by the above method is also described.
摘要翻译：半导体处理方法包括提供衬底，在衬底中形成多个半导体层，每个半导体层是不同的并且选自不同的半导体元件组，半导体层包括第一，第二和第三半导体层。该方法还包括在形成第三半导体层之前在第二半导体层上形成氮化物覆盖层。还描述了通过上述方法形成的半导体结构。

82. 发明授权

US07358164B2 Crystal imprinting methods for fabricating substrates with thin active silicon layers 失效
标题翻译：用于制造具有薄的活性硅层的衬底的晶体压印方法
公开(公告)号：US07358164B2
公开(公告)日：2008-04-15
申请号：US11154907
申请日：2005-06-16
申请人： Louis Lu-Chen Hsu , Jack Allan Mandelman , William Robert Tonti
发明人： Louis Lu-Chen Hsu , Jack Allan Mandelman , William Robert Tonti
IPC分类号： H01L21/20
CPC分类号： H01L29/045 , H01L21/84 , H01L27/1203
摘要： Methods of forming semiconductor structures characterized by a thin active silicon layer on an insulating substrate by a crystal imprinting or damascene approach. The methods include patterning an insulating layer to define a plurality of apertures, filling the apertures in the patterned insulating layer with amorphous silicon to define a plurality of amorphous silicon features, and re-growing the amorphous silicon features to define a thin active silicon layer consisting of regrown silicon features. The amorphous silicon features may be regrown such that a number have a first crystal orientation and another number have a different second crystal orientation.
摘要翻译：通过晶体压印或镶嵌法在绝缘基板上形成由活性硅层薄的特征的半导体结构的方法。所述方法包括图案化绝缘层以限定多个孔，用非晶硅填充图案化绝缘层中的孔以限定多个非晶硅特征，以及重新生长非晶硅特征以限定薄的有源硅层，的再生硅特征。可以重新生长非晶硅特征，使得数量具有第一晶体取向，而另一数目具有不同的第二晶体取向。

83. 发明授权

US07348280B2 Method for fabricating and BEOL interconnect structures with simultaneous formation of high-k and low-k dielectric regions 有权
标题翻译：同时形成高k和低k电介质区域的制造方法和BEOL互连结构
公开(公告)号：US07348280B2
公开(公告)日：2008-03-25
申请号：US11266741
申请日：2005-11-03
申请人： Louis Lu-Chen Hsu , Jack Allan Mandelman , William Tonti , Chih-Chao Yang
发明人： Louis Lu-Chen Hsu , Jack Allan Mandelman , William Tonti , Chih-Chao Yang
IPC分类号： H01L21/469
CPC分类号： H01L23/5329 , H01L21/7682 , H01L21/76849 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , Y10S438/942 , H01L2924/00
摘要： A method for fabricating and back-end-of-line (BEOL) metalization structures includes simultaneous high-k and low-k dielectric regions. An interconnect structure includes a first inter-level dielectric (ILD) layer and a second ILD layer with the first ILD layer underlying the second ILD layer. A plurality of columnar air gaps is formed in the first ILD. The columnar air gap structure is created using a two-phase photoresist material for providing different etching selectivity during subsequent processing.
摘要翻译：一种用于制造和后端（BEOL）金属化结构的方法包括同时存在的高k和低k电介质区域。互连结构包括第一层间电介质（ILD）层和具有位于第二ILD层下面的第一ILD层的第二ILD层。在第一ILD中形成多个柱状气隙。使用两相光致抗蚀剂材料制造柱状气隙结构，用于在随后的处理期间提供不同的蚀刻选择性。

84. 发明申请

US20080048259A1 Method for Reducing Defects in Buried Oxide Layers of Silicon on Insulator Substrates 审中-公开
标题翻译：减少硅绝缘体衬底氧化层缺陷的方法
公开(公告)号：US20080048259A1
公开(公告)日：2008-02-28
申请号：US11466480
申请日：2006-08-23
申请人： Kangguo Cheng , Ramachandra Divakaruni , Louis Lu-Chen Hsu , Jack Allan Mandelman
发明人： Kangguo Cheng , Ramachandra Divakaruni , Louis Lu-Chen Hsu , Jack Allan Mandelman
IPC分类号： H01L27/12
CPC分类号： H01L29/78603 , H01L29/66772 , H01L29/78609
摘要： A method and a structure for reducing defects in buried oxide layers of a silicon-on-insulator substrate. The method includes: generating a beam of infrared radiation of a selected wavelength; exposing a silicon-on-insulator substrate to the beam of infrared radiation, the substrate comprising a buried silicon dioxide layer between a lower layer of silicon and an upper layer of silicon; and wherein silicon has a transmittance of at least 95% at the selected wavelength and silicon dioxide has a transmittance of less than 80% at the selected wavelength.
摘要翻译：一种减少绝缘体上硅衬底的掩埋氧化物层缺陷的方法和结构。该方法包括：产生所选波长的红外辐射束; 将绝缘体上硅衬底暴露于所述红外辐射束，所述衬底包括在下层硅和硅上层之间的掩埋二氧化硅层; 并且其中硅在所选波长处具有至少95％的透射率，并且二氧化硅在所选择的波长处具有小于80％的透射率。

85. 发明申请

US20080003757A1 Semiconductor Device Structures for Bipolar Junction Transistors and Methods of Fabricating Such Structures 有权
标题翻译：用于双极结晶体管的半导体器件结构和制造这种结构的方法
公开(公告)号：US20080003757A1
公开(公告)日：2008-01-03
申请号：US11427982
申请日：2006-06-30
申请人： Kangguo Cheng , Louis Lu-Chen Hsu , Jack Allan Mandelman
发明人： Kangguo Cheng , Louis Lu-Chen Hsu , Jack Allan Mandelman
IPC分类号： H01L21/331
CPC分类号： H01L29/732 , H01L29/66265
摘要： Semiconductor device structures for use with bipolar junction transistors and methods of fabricating such semiconductor device structures. The semiconductor device structure comprises a semiconductor body having a top surface and sidewalls extending from the top surface to an insulating layer, a first region including a first semiconductor material with a first conductivity type, and a second region including a second semiconductor material with a second conductivity type. The first and second regions each extend across the top surface and the sidewalls of the semiconductor body. The device structure further comprises a junction defined between the first and second regions and extending across the top surface and the sidewalls of the semiconductor body.
摘要翻译：用于双极结晶体管的半导体器件结构和制造这种半导体器件结构的方法。半导体器件结构包括具有顶表面和从顶表面延伸到绝缘层的侧壁的半导体本体，包括具有第一导电类型的第一半导体材料的第一区域和包括具有第二导电类型的第二半导体材料的第二区域导电类型。第一和第二区域各自延伸穿过半导体本体的顶表面和侧壁。器件结构还包括限定在第一和第二区域之间并且跨越半导体本体的顶表面和侧壁延伸的接合部。

86. 发明授权

US07113006B2 Capacitor reliability for multiple-voltage power supply systems 失效
标题翻译：多电压电源系统的电容可靠性
公开(公告)号：US07113006B2
公开(公告)日：2006-09-26
申请号：US11065840
申请日：2005-02-25
申请人： Louis L. Hsu , Rajiv V. Joshi , Jack Allan Mandelman
发明人： Louis L. Hsu , Rajiv V. Joshi , Jack Allan Mandelman
IPC分类号： H03K5/22 , H03K5/153 , H01G23/00
CPC分类号： H02M3/07
摘要： A capacitor circuit having improved reliability includes at least first and second capacitors, a first terminal of the first capacitor connecting to a first source providing a first voltage, a first terminal of the second capacitor connecting to a second source providing a second voltage, the first voltage being greater than the second voltage. The capacitor further includes a voltage comparator having a first input for receiving a voltage representative of the first voltage, a second input for receiving a third voltage provided by a third source, and an output for generating a control signal. The control signal is a function of a difference between the voltage representative of the first voltage and the third voltage. A switch is connected to second terminals of the first and second capacitors. The switch is selectively operable in one of at least a first mode and a second mode in response to the control signal, wherein in the first mode the switch is operative to connect the first and second capacitors together in parallel, and in the second mode the switch is operative to connect the first and second capacitors together in series. The first mode is indicative of the voltage representative of the first voltage being less than or about equal to the third voltage, and the second mode is indicative of the voltage representative of the first voltage being greater than the third voltage.
摘要翻译：具有改进的可靠性的电容器电路包括至少第一和第二电容器，第一电容器的第一端子连接到提供第一电压的第一源极，第二电容器的第一端子连接到提供第二电压的第二源极，第一电容器电压大于第二电压。电容器还包括电压比较器，具有用于接收表示第一电压的电压的第一输入端，用于接收由第三源极提供的第三电压的第二输入端和用于产生控制信号的输出端。控制信号是代表第一电压和第三电压的电压之差的函数。开关连接到第一和第二电容器的第二端子。响应于控制信号，开关选择性地可操作于至少第一模式和第二模式之一中，其中在第一模式中，开关可操作以并联连接第一和第二电容器，并且在第二模式中，开关可操作以串联连接第一和第二电容器。第一模式表示代表第一电压的电压小于或等于第三电压，第二模式表示代表第一电压的电压大于第三电压。

87. 发明授权

US06818487B2 Self-aligned, planarized thin-film transistors, devices employing the same, and methods of fabrication thereof 失效
标题翻译：自对准的平面化薄膜晶体管，采用该晶体管的器件及其制造方法
公开(公告)号：US06818487B2
公开(公告)日：2004-11-16
申请号：US10631533
申请日：2003-07-31
申请人： Louis L. Hsu , Jack Allan Mandelman , William Robert Tonti , Li-Kong Wang
发明人： Louis L. Hsu , Jack Allan Mandelman , William Robert Tonti , Li-Kong Wang
IPC分类号： H01L2100
CPC分类号： H01L29/66787 , H01L27/11 , H01L27/1108 , H01L29/42384 , H01L29/66765 , H01L29/78636
摘要： A semiconductor device is presented which includes a self-aligned, planarized thin-film transistor which can be used in various integrated circuit devices, such as static random access memory (SRAM) cells. The semiconductor device has a first field-effect transistor and a second field-effect transistor. The second field-effect transistor overlies the first field-effect transistor, and the first field-effect transistor and the second field-effect transistor share a common gate. The second field-effect transistor includes a source and a drain which are self-aligned to the shared gate in a layer of planarized semiconductor material above the first field-effect transistor. In one embodiment, the second field-effect transistor is a thin-film transistor, and the shared gate has a U-shape wrap-around configuration at a body of the thin-film transistor.
摘要翻译：提出了一种半导体器件，其包括可用于诸如静态随机存取存储器（SRAM）单元的各种集成电路器件中的自对准的平坦化薄膜晶体管。半导体器件具有第一场效应晶体管和第二场效应晶体管。第二场效应晶体管覆盖第一场效应晶体管，第一场效应晶体管和第二场效应晶体管共用公共栅极。第二场效应晶体管包括在第一场效应晶体管上方的平坦化半导体材料层中与共享栅极自对准的源极和漏极。在一个实施例中，第二场效应晶体管是薄膜晶体管，并且共享栅极在薄膜晶体管的主体处具有U形环绕配置。

88. 发明授权

US06649935B2 Self-aligned, planarized thin-film transistors, devices employing the same 失效
标题翻译：自对准的平面化薄膜晶体管，采用它们的器件
公开(公告)号：US06649935B2
公开(公告)日：2003-11-18
申请号：US09795535
申请日：2001-02-28
申请人： Louis L. Hsu , Jack Allan Mandelman , William Robert Tonti , Li-Kong Wang
发明人： Louis L. Hsu , Jack Allan Mandelman , William Robert Tonti , Li-Kong Wang
IPC分类号： H01L2976
CPC分类号： H01L29/66787 , H01L27/11 , H01L27/1108 , H01L29/42384 , H01L29/66765 , H01L29/78636
摘要： A semiconductor device is presented which includes a self-aligned, planarized thin-film transistor which can be used in various integrated circuit devices, such as static random access memory (SRAM) cells. The semiconductor device has a first field-effect transistor and a second field-effect transistor. The second field-effect transistor overlies the first field-effect transistor, and the first field-effect transistor and the second field-effect transistor share a common gate. The second field-effect transistor includes a source and a drain which are self-aligned to the shared gate in a layer of planarized seminconductor material above the first field-effect transistor. In one embodiment, the second field-effect transistor is a thin-film transistor, and the shared gate has a U-shape wrap-around configuration at a body of the thin-film transistor.
摘要翻译：提出了一种半导体器件，其包括可用于诸如静态随机存取存储器（SRAM）单元的各种集成电路器件中的自对准的平坦化薄膜晶体管。半导体器件具有第一场效应晶体管和第二场效应晶体管。第二场效应晶体管覆盖第一场效应晶体管，第一场效应晶体管和第二场效应晶体管共用公共栅极。第二场效应晶体管包括在第一场效应晶体管之上的平坦化半导体材料层中与共享栅极自对准的源极和漏极。在一个实施例中，第二场效应晶体管是薄膜晶体管，并且共享栅极在薄膜晶体管的主体处具有U形环绕配置。

89. 发明授权

US06531410B2 Intrinsic dual gate oxide MOSFET using a damascene gate process 有权
公开(公告)号：US06531410B2
公开(公告)日：2003-03-11
申请号：US09795610
申请日：2001-02-27
申请人： Claude Louis Bertin , Anthony J. Dally , John Atkinson Fifield , John Jesse Higgins , Jack Allan Mandelman , William Robert Tonti , Nicholas Martin van Heel
发明人： Claude Louis Bertin , Anthony J. Dally , John Atkinson Fifield , John Jesse Higgins , Jack Allan Mandelman , William Robert Tonti , Nicholas Martin van Heel
IPC分类号： H01L2131
CPC分类号： H01L21/2822 , H01L21/2255 , H01L21/26506 , H01L21/26533 , H01L21/28238 , H01L21/823462 , H01L29/42368 , H01L29/511 , H01L29/6653 , H01L29/66553 , H01L29/66583 , H01L29/66613 , H01L29/7834
摘要： Damascene or non-damascene processing when used with a method that includes (a) forming a mask having an opening therethrough on a structure, said opening having sidewalls; (b) implanting an inhibiting species into said structure through the opening so as to form an inhibiting region in said structure; and (c) growing a dielectric layer on the structure in said opening, wherein the inhibiting region partially inhibits growth of the dielectric layer is capable of forming a semiconductor structure, e.g., MOSFET or anti-fuse, including a dual thickness dielectric layer. Alternatively, the dual thickness dielectric can be formed by replacing the inhibiting species mentioned above with a dielectric growth enhancement species which forms an enhancing region in the structure which aids in the growth of the dielectric layer.

90. 发明授权

US6153474A Method of controllably forming a LOCOS oxide layer over a portion of a vertically extending sidewall of a trench extending into a semiconductor substrate 失效
标题翻译：在延伸到半导体衬底的沟槽的垂直延伸的侧壁的一部分上可控地形成LOCOS氧化物层的方法
公开(公告)号：US6153474A
公开(公告)日：2000-11-28
申请号：US108619
申请日：1998-07-01
申请人： Herbert Lei Ho , Radhika Srinivasan , Scott D. Halle , Erwin Hammerl , David M. Dobuzinsky , Jack Allan Mandelman , Mark Anthony Jaso
发明人： Herbert Lei Ho , Radhika Srinivasan , Scott D. Halle , Erwin Hammerl , David M. Dobuzinsky , Jack Allan Mandelman , Mark Anthony Jaso
IPC分类号： H01L27/04 , H01L21/02 , H01L21/762 , H01L21/822 , H01L21/8242 , H01L27/108 , H01L21/336
CPC分类号： H01L27/10861 , H01L21/76232 , H01L27/10832 , H01L28/82 , Y10S438/973
摘要： The present invention includes a method and system to increase the deep trench sidewall surface area in a storage node on a DRAM chip. By tilting the trenches the capacitance is increased without taking up more space on the semiconductor chip.
摘要翻译：本发明包括一种用于增加DRAM芯片上的存储节点中的深沟槽侧壁表面积的方法和系统。通过倾斜沟槽，电容增加，而不占用半导体芯片上的更多空间。

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