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81. 发明授权

US07949983B2 High tolerance TCR balanced high current resistor for RF CMOS and RF SiGe BiCMOS applications and cadenced based hierarchical parameterized cell design kit with tunable TCR and ESD resistor ballasting feature 有权
标题翻译：高容差TCR平衡型高电流电阻，用于射频CMOS和射频SiGe BiCMOS应用以及基于分级的分级参数化电池设计套件，具有可调TCR和ESD电阻镇流功能
公开(公告)号：US07949983B2
公开(公告)日：2011-05-24
申请号：US12234473
申请日：2008-09-19
申请人： Ebenezer E. Eshun , Steven H. Voldman
发明人： Ebenezer E. Eshun , Steven H. Voldman
IPC分类号： G06F17/50
CPC分类号： H01C7/06 , H01L27/0288 , H01L27/0802 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： A resistor device structure and method of manufacture therefore, wherein the resistor device structure invention includes a plurality of alternating conductive film and insulative film layers, at least two of the conductive film layers being electrically connected in parallel to provide for high current flow through the resistor device at high frequencies with increased temperature and mechanical stability. The alternating conductive film and insulative film layers may be of a planar or non-planar geometric spatial orientation. The alternating conductive film and insulative film layers may include lateral and vertical portions designed to enable a uniform current density flow within the structure itself through a self-ballasting effect within the physical resistor. A computer aided design tool with graphical and schematic features is provided to enable generation of hierarchical parameterized cells for a resistor element with the ability to provide customization, personalization and tunability of TCR, TCR matching, and high current and ESD robustness.
摘要翻译：因此，电阻器件结构及其制造方法，其中电阻器件结构发明包括多个交替导电膜和绝缘膜层，至少两个导电膜层并联电连接以提供通过电阻器的高电流器件在高频下具有升高的温度和机械稳定性。交替导电膜和绝缘膜层可以是平面或非平面的几何空间取向。交替导电膜和绝缘膜层可以包括横向和垂直部分，其被设计成能够通过物理电阻器内的自镇流效应在结构本身内实现均匀的电流密度流动。提供了具有图形和原理图功能的计算机辅助设计工具，以便能够为电阻元件生成分层参数化单元，具有提供TCR，TCR匹配以及高电流和ESD鲁棒性的定制，个性化和可调性的能力。

82. 发明申请

US20090019414A1 HIGH TOLERANCE TCR BALANCED HIGH CURRENT RESISTOR FOR RF CMOS AND RF SIGE BICMOS APPLICATIONS AND CADENCED BASED HIERARCHICAL PARAMETERIZED CELL DESIGN KIT WITH TUNABLE TCR AND ESD RESISTOR BALLASTING FEATURE 有权
标题翻译：用于RF CMOS和RF SIGE BICMOS应用的高耐压TCR平衡型高电流电阻器和基于CAD的分层式参考电池设计套件，具有TUNABLE TCR和ESD电阻贴片特性
公开(公告)号：US20090019414A1
公开(公告)日：2009-01-15
申请号：US12234473
申请日：2008-09-19
申请人： Ebenezer E. Eshun , Steven H. Voldman
发明人： Ebenezer E. Eshun , Steven H. Voldman
IPC分类号： G06F17/50
CPC分类号： H01C7/06 , H01L27/0288 , H01L27/0802 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： A resistor device structure and method of manufacture therefore, wherein the resistor device structure invention includes a plurality of alternating conductive film and insulative film layers, at least two of the conductive film layers being electrically connected in parallel to provide for high current flow through the resistor device at high frequencies with increased temperature and mechanical stability. The alternating conductive film and insulative film layers may be of a planar or non-planar geometric spatial orientation. The alternating conductive film and insulative film layers may include lateral and vertical portions designed to enable a uniform current density flow within the structure itself through a self-ballasting effect within the physical resistor. A computer aided design tool with graphical and schematic features is provided to enable generation of hierarchical parameterized cells for a resistor element with the ability to provide customization, personalization and tunability of TCR, TCR matching, and high current and ESD robustness.
摘要翻译：因此，电阻器件结构及其制造方法，其中电阻器件结构发明包括多个交替导电膜和绝缘膜层，至少两个导电膜层并联电连接以提供通过电阻器的高电流器件在高频下具有升高的温度和机械稳定性。交替导电膜和绝缘膜层可以是平面或非平面的几何空间取向。交替导电膜和绝缘膜层可以包括横向和垂直部分，其被设计成能够通过物理电阻器内的自镇流效应在结构本身内实现均匀的电流密度流动。提供了具有图形和原理图功能的计算机辅助设计工具，以便能够为电阻元件生成分层参数化单元，具有提供TCR，TCR匹配以及高电流和ESD鲁棒性的定制，个性化和可调性的能力。

83. 发明授权

US07427550B2 Methods of fabricating passive element without planarizing 有权
标题翻译：无平面化制造无源元件的方法
公开(公告)号：US07427550B2
公开(公告)日：2008-09-23
申请号：US11427457
申请日：2006-06-29
申请人： Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Anthony K. Stamper , Kunal Vaed
发明人： Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Anthony K. Stamper , Kunal Vaed
IPC分类号： H01L21/20
CPC分类号： H01L21/76819 , H01L23/522 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.
摘要翻译：公开了制造无源元件的方法和包括无源元件的半导体器件，其包括使用虚拟无源元件。虚拟无源元件是被添加到芯片布局以帮助平坦化但在有源电路中不使用的无源元件或线。该方法的一个实施例包括形成无源元件和邻近无源元件的虚拟无源元件; 在无源元件和虚拟无源元件上形成电介质层，其中介电层在无源元件和虚拟无源元件之间基本上是平面的; 并且在电介质层中形成通过电介质层与无源元件的互连以及与虚拟无源元件的至少一部分重叠的虚拟互连部分。该方法消除了平面化的需要。

84. 发明授权

US07145218B2 Thin-film resistor and method of manufacturing the same 有权
标题翻译：薄膜电阻及其制造方法
公开(公告)号：US07145218B2
公开(公告)日：2006-12-05
申请号：US10709692
申请日：2004-05-24
申请人： Ebenezer E. Eshun
发明人： Ebenezer E. Eshun
IPC分类号： H01L29/00
CPC分类号： H01L23/5228 , H01C1/142 , H01C7/006 , H01L27/016 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： The invention relates to integration of a thin-film resistor in a wiring level, such as, for example, an aluminum back-end-of-line (BEOL) technology. The thin-film resistor is formed in a wiring level on, for example, an upper surface of a dielectric layer. The thin-film resistor includes end portions tapered at an angle less than 90 degrees with respect to the upper surface. The tapered end portions provide increased surface area for making contact to the thin-film resistor without adversely affecting the resistance value of the thin-film resistor.
摘要翻译：本发明涉及薄膜电阻器在布线层中的集成，例如铝后端（BEOL）技术。薄膜电阻器形成在例如电介质层的上表面上的布线层中。薄膜电阻器包括相对于上表面以小于90度的角度渐缩的端部。锥形端部提供增加的表面积，用于与薄膜电阻器接触，而不会不利地影响薄膜电阻器的电阻值。

85. 发明授权

US08569840B2 Bipolar transistor integrated with metal gate CMOS devices 失效
标题翻译：与金属栅极CMOS器件集成的双极晶体管
公开(公告)号：US08569840B2
公开(公告)日：2013-10-29
申请号：US13370523
申请日：2012-02-10
申请人： Thomas A. Wallner , Ebenezer E. Eshun , Daniel J. Jaeger , Phung T. Nguyen
发明人： Thomas A. Wallner , Ebenezer E. Eshun , Daniel J. Jaeger , Phung T. Nguyen
IPC分类号： H01L29/70 , H01L29/73 , H01L29/78
CPC分类号： H01L21/8249 , H01L27/0623
摘要： A high-k gate dielectric layer and a metal gate layer are formed and patterned to expose semiconductor surfaces in a bipolar junction transistor region, while covering a CMOS region. A disposable material portion is formed on a portion of the exposed semiconductor surfaces in the bipolar junction transistor area. A semiconductor layer and a dielectric layer are deposited and patterned to form gate stacks including a semiconductor portion and a dielectric gate cap in the CMOS region and a cavity containing mesa over the disposable material portion in the bipolar junction transistor region. The disposable material portion is selectively removed and a base layer including an epitaxial portion and a polycrystalline portion fills the cavity formed by removal of the disposable material portion. The emitter formed by selective epitaxy fills the cavity in the mesa.
摘要翻译：形成高k栅极电介质层和金属栅极层，并图案化以暴露双极结型晶体管区域中的半导体表面，同时覆盖CMOS区域。一次性材料部分形成在双极结型晶体管区域中暴露的半导体表面的一部分上。沉积半导体层和电介质层，以形成包括CMOS区域中的半导体部分和介电栅极盖的栅极堆叠，以及在双极结型晶体管区域中的一次性材料部分上的包含台面的空腔。选择性地去除一次性材料部分，并且包括外延部分和多晶部分的基层填充通过去除一次性材料部分而形成的空腔。通过选择性外延形成的发射体填充台面中的空腔。

86. 发明授权

US08487401B2 Methods of fabricating passive element without planarizing and related semiconductor device 有权
标题翻译：无平面化制造无源元件及相关半导体器件的方法
公开(公告)号：US08487401B2
公开(公告)日：2013-07-16
申请号：US13359634
申请日：2012-01-27
申请人： Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Anthony K. Stamper , Kunal Vaed
发明人： Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Anthony K. Stamper , Kunal Vaed
IPC分类号： H01L23/522
CPC分类号： H01L21/76819 , H01L23/522 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.
摘要翻译：公开了制造无源元件的方法和包括无源元件的半导体器件，其包括使用虚拟无源元件。虚拟无源元件是被添加到芯片布局以帮助平坦化但在有源电路中不使用的无源元件或线。该方法的一个实施例包括形成无源元件和邻近无源元件的虚拟无源元件; 在无源元件和虚拟无源元件上形成电介质层，其中介电层在无源元件和虚拟无源元件之间基本上是平面的; 并且在电介质层中形成通过电介质层与无源元件的互连以及与虚拟无源元件的至少一部分重叠的虚拟互连部分。该方法消除了平面化的需要。

87. 发明授权

US08119491B2 Methods of fabricating passive element without planarizing and related semiconductor device 有权
标题翻译：无平面化制造无源元件及相关半导体器件的方法
公开(公告)号：US08119491B2
公开(公告)日：2012-02-21
申请号：US12106374
申请日：2008-04-21
申请人： Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Anthony K. Stamper , Kunal Vaed
发明人： Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Anthony K. Stamper , Kunal Vaed
IPC分类号： H01L21/20
CPC分类号： H01L21/76819 , H01L23/522 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.
摘要翻译：公开了制造无源元件的方法和包括无源元件的半导体器件，其包括使用虚拟无源元件。虚拟无源元件是被添加到芯片布局以帮助平坦化但在有源电路中不使用的无源元件或线。该方法的一个实施例包括形成无源元件和邻近无源元件的虚拟无源元件; 在无源元件和虚拟无源元件上形成电介质层，其中介电层在无源元件和虚拟无源元件之间基本上是平面的; 并且在电介质层中形成通过电介质层与无源元件的互连以及与虚拟无源元件的至少一部分重叠的虚拟互连部分。该方法消除了平面化的需要。

88. 发明授权

US07825441B2 Junction field effect transistor with a hyperabrupt junction 有权
标题翻译：结型场效应晶体管具有超级连接
公开(公告)号：US07825441B2
公开(公告)日：2010-11-02
申请号：US11767627
申请日：2007-06-25
申请人： Ebenezer E. Eshun , Jeffrey B. Johnson , Richard A. Phelps , Robert M. Rassel , Michael J. Zierak
发明人： Ebenezer E. Eshun , Jeffrey B. Johnson , Richard A. Phelps , Robert M. Rassel , Michael J. Zierak
IPC分类号： H01L29/808 , H01L21/337
CPC分类号： H01L29/808 , H01L27/0617 , H01L27/098 , H01L29/36 , H01L29/66901
摘要： A junction field effect transistor (JFET) has a hyperabrupt junction layer that functions as a channel of a JFET. The hyperabrupt junction layer is formed by two dopant profiles of opposite types such that one dopant concentration profile has a peak concentration depth at a tail end of the other dopant profile. The voltage bias to the channel is provided by a body that is doped with the same type of dopants as the gate. This is in contrast with conventional JFETs that have a body that is doped with the opposite conductivity type as the gate. The body may be electrically decoupled from the substrate by another reverse bias junction formed either between the body and the substrate or between a buried conductor layer beneath the body and the substrate. The capability to form a thin hyperabrupt junction layer allows formation of a JFET in a semiconductor-on-insulator substrate.
摘要翻译：结型场效应晶体管（JFET）具有作为JFET通道的超破裂结层。超破裂结层由相反类型的两个掺杂剂分布形成，使得一个掺杂剂浓度分布在另一个掺杂剂分布的尾端处具有峰值浓度深度。通道的电压偏置由掺杂有与栅极相同类型的掺杂剂的主体提供。这与传统的JFET相反，JFET具有以与栅极相反的导电类型掺杂的主体。主体可以通过形成在主体和衬底之间或者在主体和衬底之下的掩埋导体层之间形成的另一反向偏压接合部与衬底电耦合。形成薄的超破裂结层的能力允许在绝缘体上半导体衬底中形成JFET。

89. 发明授权

US07585722B2 Integrated circuit comb capacitor 有权
标题翻译：集成电路梳状电容
公开(公告)号：US07585722B2
公开(公告)日：2009-09-08
申请号：US11306746
申请日：2006-01-10
申请人： Daniel C. Edelstein , Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Sarah L. Lane , Anthony K. Stamper
发明人： Daniel C. Edelstein , Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Sarah L. Lane , Anthony K. Stamper
IPC分类号： H01L29/00
CPC分类号： H01L23/5223 , H01L21/76814 , H01L21/76816 , H01L21/76831 , H01L28/87 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The invention is directed to an integrated circuit comb capacitor with capacitor electrodes that have an increased capacitance between neighboring capacitor electrodes as compared with other interconnects and via contacts formed in the same metal wiring level and at the same pitches. The invention achieves a capacitor that minimizes capacitance tolerance and preserves symmetry in parasitic electrode-substrate capacitive coupling, without adversely affecting other interconnects and via contacts formed in the same wiring level, through the use of, at most, one additional noncritical, photomask.
摘要翻译：本发明涉及具有电容器电极的集成电路梳状电容器，其与在相同金属布线级别和相同间距处形成的其它互连和通孔触点相比，在相邻的电容器电极之间具有增加的电容。本发明实现了一种电容器，其使电容容限最小化并且在寄生电极 - 基板电容耦合中保持对称性，而不会通过使用至多一个附加的非临界光掩模来不利地影响在相同布线级别形成的其它互连和通孔触点。

90. 发明申请

US20080003759A1 METHODS OF FABRICATING PASSIVE ELEMENT WITHOUT PLANARIZING AND RELATED SEMICONDUCTOR DEVICE 有权
公开(公告)号：US20080003759A1
公开(公告)日：2008-01-03
申请号：US11427457
申请日：2006-06-29
申请人： Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Anthony K. Stamper , Kunal Vaed
发明人： Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Anthony K. Stamper , Kunal Vaed
IPC分类号： H01L21/20
CPC分类号： H01L21/76819 , H01L23/522 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.

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