专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明授权

US07188266B1 Systems and methods for reducing static and total power consumption in a programmable logic device 有权
标题翻译：用于减少可编程逻辑器件中的静态和总功耗的系统和方法
公开(公告)号：US07188266B1
公开(公告)日：2007-03-06
申请号：US10796501
申请日：2004-03-08
申请人： David Mendel , Vaughn Betz
发明人： David Mendel , Vaughn Betz
IPC分类号： G06F1/26 , G06F1/32 , H03K19/173
CPC分类号： G06F1/32
摘要： A method and system for reducing power consumption in a programmable logic device (PLD) is provided. The power consumption may be reduced by preferably continually considering power consumption as a factor in circuit design during the technology mapping, routing, and period following routing of the programmable logic device.
摘要翻译：提供了一种用于降低可编程逻辑器件（PLD）中功耗的方法和系统。在可编程逻辑器件的技术映射，路由和后续周期期间，优选地可以连续地考虑功率消耗作为电路设计中的一个因素来降低功耗。

82. 发明授权

US07138844B2 Variable delay circuitry 有权
标题翻译：可变延迟电路
公开(公告)号：US07138844B2
公开(公告)日：2006-11-21
申请号：US11083482
申请日：2005-03-18
申请人： Andy L. Lee , Gary Lai , Changsong Zhang , Vaughn Betz , Ryan Fung
发明人： Andy L. Lee , Gary Lai , Changsong Zhang , Vaughn Betz , Ryan Fung
IPC分类号： H03H11/26
CPC分类号： H03K5/133 , H03K2005/00058
摘要： Circuitry for providing an input data signal to other circuitry on an integrated circuit includes a course delay chain and a fine delay chain. These two delay chains are cascadable, if desired, to provide a very wide range of possible amounts of delay which can be finely graded by use of the fine delay chain.
摘要翻译：用于向集成电路上的其它电路提供输入数据信号的电路包括一个课程延迟链和一个精细延迟链。如果需要，这两个延迟链是可级联的，以提供可以通过使用精细延迟链精细分级的可能的延迟量的非常宽的范围。

83. 发明申请

US20060225021A1 Automatic adjustment of optimization effort in configuring programmable devices 有权
标题翻译：自动调整配置可编程设备的优化工作
公开(公告)号：US20060225021A1
公开(公告)日：2006-10-05
申请号：US11097592
申请日：2005-04-01
申请人： Ketan Padalia , Jason Peters , Vaughn Betz
发明人： Ketan Padalia , Jason Peters , Vaughn Betz
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： User designs are assigned to a category for each design goal associated with the user design. Each category represents the difficulty of satisfying a design goal. Optimization phases are tailored to different combinations of categories and are selected according to the categories assigned to the user design. A ranking of the relative difficulty of the design goals is determined from the categories associated with the user design. Parameters of an optimization phase can be modified in accordance with this ranking to focus optimization efforts on specific design goals. The parameters may be weights of a cost function used by the optimization phase to evaluate alternative configurations of the user design. The user design can be re-classified into an additional category if the results of the optimization phase do not satisfy design goals, and additional optimization phases are selected based on this re-classification to further optimize the user design.
摘要翻译：用户设计被分配到与用户设计相关联的每个设计目标的类别。每个类别代表满足设计目标的难度。优化阶段根据类别的不同组合进行调整，并根据分配给用户设计的类别进行选择。根据与用户设计相关的类别确定设计目标相对难度的排名。优化阶段的参数可以根据这个排名进行修改，将优化工作集中在具体的设计目标上。参数可以是优化阶段用于评估用户设计的替代配置的成本函数的权重。如果优化阶段的结果不满足设计目标，则可以将用户设计重新分类为另外的类别，并且基于该重新分类来选择额外的优化阶段以进一步优化用户设计。

84. 发明授权

US06590419B1 Heterogeneous interconnection architecture for programmable logic devices 有权
标题翻译：用于可编程逻辑器件的异构互连架构
公开(公告)号：US06590419B1
公开(公告)日：2003-07-08
申请号：US09478097
申请日：1999-10-12
申请人： Vaughn Betz , Jonathan Rose
发明人： Vaughn Betz , Jonathan Rose
IPC分类号： H03K19177
CPC分类号： H03K19/17736 , H03K19/17704
摘要： An interconnection architecture for programmable logic devices (PLDs) is presented in which heterogeneous interconnect resources can be programmably connected to function blocks in accordance with two or more operational parameters, such as, for example, signal propagation speed, circuit area, signal routing flexibility, and PLD reliability. Programmable interconnect resources include unbalanced multiplexers, different types of interface buffers, and signal wires of different widths and different wire-to-wire spacings.
摘要翻译：提出了一种用于可编程逻辑器件（PLD）的互连结构，其中异构互连资源可以根据两个或多个操作参数（例如信号传播速度，电路面积，信号路由灵活性）可编程地连接到功能块，和PLD可靠性。可编程互连资源包括不平衡多路复用器，不同类型的接口缓冲器和不同宽度和不同线对线间距的信号线。

85. 发明授权

US5537341A Complementary architecture for field-programmable gate arrays 失效
标题翻译：现场可编程门阵列的互补架构
公开(公告)号：US5537341A
公开(公告)日：1996-07-16
申请号：US387402
申请日：1995-02-10
申请人： Jonathan Rose , Vaughn Betz
发明人： Jonathan Rose , Vaughn Betz
IPC分类号： G06F17/50 , G06F17/00
CPC分类号： G06F17/5054
摘要： The use of more than one field-programmable gate array design with a given logic capacity produces advantages over the use of a single field-programmable gate array design. The designs of the field-programmable gate arrays in the family are be selected so that each field-programmable gate array design advantageously implements a different type of circuit. This use can select from the family of FPGAs with the same logic capacity such that the circuits can on average be implemented faster and/or in a smaller area.
摘要翻译：使用具有给定逻辑容量的多个现场可编程门阵列设计产生优于使用单个现场可编程门阵列设计的优点。可以选择族中的现场可编程门阵列的设计，使得每个现场可编程门阵列设计有利地实现不同类型的电路。这种使用可以从具有相同逻辑容量的FPGA系列中进行选择，使得电路平均可以更快地实现和/或在较小的区域中实现。

86. 发明授权

US11018668B2 Characterization of power delivery network in field programmable gate arrays or digital integrated circuits 有权
公开(公告)号：US11018668B2
公开(公告)日：2021-05-25
申请号：US16190987
申请日：2018-11-14
申请人： Shuze Zhao , Olivier Trescases , Ibrahim Ahmed , Vaughn Betz , THE GOVERNING COUNCIL OF THE UNIVERSITY OF TORONTO
发明人： Shuze Zhao , Olivier Trescases , Ibrahim Ahmed , Vaughn Betz
IPC分类号： H03K19/00 , H03K19/003 , H03M7/16 , H03M1/12 , H03M1/50
摘要： Modern FPGAs operate at a core voltage around 1V and therefore even small voltage fluctuations can lead to timing violations and logic errors. The Power Delivery Network (PDN) between a power supply and the FPGA core must be carefully designed to achieve a low output impedance over a broad range of frequencies. The present disclosure describes two techniques for characterization of the PDN: 1) to extract the DC resistance in the power delivery path, and 2) to identify the high impedance frequency band(s) in the PDN. An embedded impedance extraction tool is synthesized within the FPGA load, in coordination with a mixed-signal current-mode dc-dc converter. A self-calibrated Carry-Chain based ADC (CC-ADC) is used for high-speed sampling of the core voltage. By modifying the PDN based on the extracted results, the voltage operating range and reliability of a crossbar application may be greatly extended.

87. 发明授权

US08732639B1 Method and apparatus for protecting, optimizing, and reporting synchronizers 有权
标题翻译：用于保护，优化和报告同步器的方法和装置
公开(公告)号：US08732639B1
公开(公告)日：2014-05-20
申请号：US12384377
申请日：2009-04-03
申请人： Ryan Fung , Vaughn Betz , David Neto
发明人： Ryan Fung , Vaughn Betz , David Neto
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5045 , G06F17/5031 , G06F17/505 , G06F17/5054 , G06F2217/84
摘要： A method for designing a system on a target device using an electronic design automation (EDA) tool including identifying synchronizer chains in a system design using timing relationships. According to one embodiment of the present invention, the method includes conveniently reporting system reliability considering synchronization, and automatically protecting and optimizing synchronizer chains to improve system robustness.
摘要翻译：一种使用电子设计自动化（EDA）工具在目标设备上设计系统的方法，包括使用定时关系在系统设计中识别同步器链。根据本发明的一个实施例，该方法包括方便地报告考虑同步的系统可靠性，并且自动保护和优化同步器链以提高系统的鲁棒性。

88. 发明授权

US08671377B2 Method and apparatus for placement and routing of partial reconfiguration modules 有权
标题翻译：部分重新配置模块的放置和路由的方法和装置
公开(公告)号：US08671377B2
公开(公告)日：2014-03-11
申请号：US13040255
申请日：2011-03-03
申请人： David Samuel Goldman , Mark Bourgeault , Vaughn Betz , Alan Louis Herrmann
发明人： David Samuel Goldman , Mark Bourgeault , Vaughn Betz , Alan Louis Herrmann
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5054 , G06F17/5072 , G06F2217/72
摘要： A method for designing a system on a target device includes assigning resources on the target device to static logic modules and partial reconfigurable (PR) modules in the system. The instances of one of the PR modules are placed and routed in parallel utilizing resources from those that are assigned. Other embodiments are also disclosed.
摘要翻译：用于在目标设备上设计系统的方法包括将目标设备上的资源分配给系统中的静态逻辑模块和部分可重新配置（PR）模块。其中一个PR模块的实例使用分配的那些资源进行并行布置和路由。还公开了其他实施例。

89. 发明申请

US20130007689A1 Method and Apparatus For Performing Parallel Routing Using A Multi-Threaded Routing Procedure 有权
标题翻译：使用多线程路由程序执行并行路由的方法和装置
公开(公告)号：US20130007689A1
公开(公告)日：2013-01-03
申请号：US13615563
申请日：2012-09-13
申请人： Vaughn Betz , Jordan Swartz , Vadim Gouterman
发明人： Vaughn Betz , Jordan Swartz , Vadim Gouterman
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method for designing a system to be implemented on a target device includes generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing its corresponding net. The nets in the system are assigned to a plurality of threads to be routed. The threads are executed so that a plurality of the nets are routed in parallel within their corresponding bounding box.
摘要翻译：一种用于设计要在目标设备上实现的系统的方法包括在系统中为网络生成目标设备上的边界框，其中边界框标识可用于路由其相应网络的路由资源。系统中的网络被分配给要路由的多个线程。执行线程使得多个网络在其对应的边界框内并行路由。

90. 发明申请

US20120227026A1 Method and Apparatus for Placement and Routing of Partial Reconfiguration Modules 有权
标题翻译：部分重新配置模块的放置和路由的方法和装置
公开(公告)号：US20120227026A1
公开(公告)日：2012-09-06
申请号：US13040255
申请日：2011-03-03
申请人： David Samuel Goldman , Mark Bourgeault , Vaughn Betz , Alan Louis Herrmann
发明人： David Samuel Goldman , Mark Bourgeault , Vaughn Betz , Alan Louis Herrmann
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5054 , G06F17/5072 , G06F2217/72
摘要： A method for designing a system on a target device includes assigning resources on the target device to static logic modules and partial reconfigurable (PR) modules in the system. The instances of one of the PR modules are placed and routed in parallel utilizing resources from those that are assigned. Other embodiments are also disclosed.
摘要翻译：用于在目标设备上设计系统的方法包括将目标设备上的资源分配给系统中的静态逻辑模块和部分可重新配置（PR）模块。其中一个PR模块的实例使用分配的那些资源进行并行布置和路由。还公开了其他实施例。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式