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81. 发明授权

US06643743B1 Stream-down prefetching cache 失效
标题翻译：流式预取缓存
公开(公告)号：US06643743B1
公开(公告)日：2003-11-04
申请号：US09541392
申请日：2000-03-31
申请人： Herbert Hing-Jing Hum , Zohar Bogin
发明人： Herbert Hing-Jing Hum , Zohar Bogin
IPC分类号： G06F1200
CPC分类号： G06F12/0862 , G06F2212/6026
摘要： An apparatus and method for prefetching cache data in response to data requests. The prefetching uses the memory addresses of requested data to search for other data, from a related address, in a cache. This, or other data, may then be prefetched based on the result of the search.
摘要翻译：一种用于响应于数据请求预取缓存数据的装置和方法。预取使用请求的数据的存储器地址从缓存中的相关地址搜索其他数据。然后可以基于搜索的结果来预取这个或其他数据。

82. 发明授权

US06314497B1 Apparatus and method for maintaining cache coherency in a memory system 有权
标题翻译：用于在存储器系统中维持高速缓存一致性的装置和方法
公开(公告)号：US06314497B1
公开(公告)日：2001-11-06
申请号：US09205646
申请日：1998-12-03
申请人： Steve J. Clohset , Narendra S. Khandekar , Zohar Bogin
发明人： Steve J. Clohset , Narendra S. Khandekar , Zohar Bogin
IPC分类号： G06F1212
CPC分类号： G06F12/0835 , G06F12/0804
摘要： According to one embodiment, a computer system is disclosed. The computer system includes a processor, a memory, an inverting device, a storage device coupled to the inverting device and a device coupled to the storage device. The device receives byte enable information and inverted information and provides inverted byte enable information to the memory upon a write back operation to the memory.
摘要翻译：根据一个实施例，公开了一种计算机系统。计算机系统包括处理器，存储器，反相装置，耦合到反相装置的存储装置和耦合到存储装置的装置。该设备接收字节使能信息和反相信息，并且在对存储器的回写操作时向存储器提供反转字节使能信息。

83. 发明授权

US06202112B1 Arbitration methods to avoid deadlock and livelock when performing transactions across a bridge 有权
标题翻译：仲裁方法，以避免跨越桥梁进行交易时的僵局和活锁
公开(公告)号：US06202112B1
公开(公告)日：2001-03-13
申请号：US09205351
申请日：1998-12-03
申请人： Ashish Gadagkar , Zohar Bogin , Narendra Khandekar , David D. Lent
发明人： Ashish Gadagkar , Zohar Bogin , Narendra Khandekar , David D. Lent
IPC分类号： G06F1342
CPC分类号： G06F13/4036
摘要： An embodiment of the invention is directed at a bridge having an outbound pipe for buffering transaction information and data being transported from various devices to a bus. The bridge has an arbiter for granting requests associated with these devices to access the outbound pipe for transferring the transaction information and data into the pipe. The bridge generates a reject signal in response to an initial request associated with an initial transaction from a first one of the devices if the outbound pipe is unavailable to accept further transaction information or data. The bridge has response control logic for generating a retry response for the initial transaction in response to the reject signal. The bridge is able to assert a stamp signal in response to the reject signal. The arbiter in response to the stamp being asserted waits, without granting any other lower priority requests to access the outbound pipe, until a subsequent transaction from the first device makes progress.
摘要翻译：本发明的一个实施例涉及一种具有用于缓冲交易信息和从各种设备传输到总线的数据的出站管的桥。桥接器具有用于授予与这些设备相关联的请求的仲裁器以访问出站管道，用于将事务信息和数据传送到管道中。如果出站管道不可用于接受进一步的交易信息或数据，则桥接器响应于与来自第一设备的初始事务相关联的初始请求生成拒绝信号。桥接器具有用于响应于拒绝信号而产生用于初始事务的重试响应的响应控制逻辑。桥接器能够响应于拒绝信号来声明印记信号。响应于该邮票被断言的仲裁者等待，而不允许任何其他较低优先级的请求访问出站管道，直到来自第一个设备的后续事务进行。

84. 发明授权

US06173217B2 Method and apparatus to control core logic temperature 失效
标题翻译：控制核心逻辑温度的方法和装置
公开(公告)号：US06173217B2
公开(公告)日：2001-01-09
申请号：US08990711
申请日：1997-12-15
申请人： Zohar Bogin , Vincent E. VonBokern
发明人： Zohar Bogin , Vincent E. VonBokern
IPC分类号： G05D2300
CPC分类号： G11C5/06 , G06F1/206 , G06F13/161 , G11C5/04 , G11C5/143 , G11C8/20
摘要： A method for controlling core logic temperature. The core logic having a memory controller and memory components coupled to system memory. The method having the step of determining access rate to the system memory through the core logic and controlling the temperature of the core logic by adjusting the access rate.
摘要翻译：一种控制核心逻辑温度的方法。核心逻辑具有存储器控制器和耦合到系统存储器的存储器组件。该方法具有通过核心逻辑确定对系统存储器的访问速率并通过调整访问速率来控制核心逻辑的温度的步骤。

85. 发明授权

US5551044A Method and apparatus for interrupt/SMI# ordering 失效
标题翻译：中断/ SMI＃排序的方法和装置
公开(公告)号：US5551044A
公开(公告)日：1996-08-27
申请号：US349065
申请日：1994-12-01
申请人： Nilesh V. Shah , Jeffrey L. Rabe , Zohar Bogin
发明人： Nilesh V. Shah , Jeffrey L. Rabe , Zohar Bogin
IPC分类号： G06F13/24 , G06F13/00
CPC分类号： G06F13/24
摘要： A circuit for controlling interrupt request signal transmission in a computer system. An input receives an interrupt request from an external component. First circuitry coupled to the input generates a signal in response to the interrupt request from the external component. The signal causes a processor to switch to fully operational mode. Second circuitry coupled to the input generates an interrupt request signal to the processor in response to the interrupt request from the external component. A signal processing circuit coupled to the second circuitry suppresses transmission of the interrupt request signal to the processor until the signal is transmitted to the processor.
摘要翻译：用于控制计算机系统中的中断请求信号传输的电路。输入接收来自外部组件的中断请求。耦合到输入的第一电路响应于来自外部组件的中断请求而生成信号。信号使处理器切换到完全运行模式。耦合到输入的第二电路响应于来自外部组件的中断请求，向处理器生成中断请求信号。耦合到第二电路的信号处理电路抑制中断请求信号到处理器的传输，直到信号被发送到处理器。

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