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    • 83. 发明授权
    • Packet-switched network synchronization system and method
    • 分组交换网络同步系统和方法
    • US07664144B2
    • 2010-02-16
    • US11614875
    • 2006-12-21
    • John FansonYu Wang
    • John FansonYu Wang
    • H04J3/06
    • H04L7/042H04L27/2656H04L27/2689
    • A synchronization system and method for use in a packet switched communication network are provided. The synchronization system comprises a transmitter-identification system, a packet-boundary detection system and a storage-access system. The transmitter-identification system enables each receiving terminal within the network to know the identity of the originating transmitter terminal for a given packet of information, prior to the reception of this packet of information. The packet-boundary detection system enables detection of packet synchronization parameters for all transmitter-receiver pairs of terminals within the network. The storage-access system stores the detected packet synchronization parameters and allows the receiver to access the packet synchronization parameters. According to one embodiment of the invention, the synchronization method comprises the step of detecting synchronization parameters and, for a given receiver terminal, establishing the identity of the originating transmitter for an incoming packet of information, accessing synchronization parameters corresponding to the identified transmitter, adjusting receiver based on accessed synchronization parameters and decoding the incoming packet of information.
    • 提供了一种在分组交换通信网络中使用的同步系统和方法。 同步系统包括发射机识别系统,分组边界检测系统和存储接入系统。 在接收到该信息包之前,发射机识别系统使得网络内的每个接收终端能够知道给定分组信息的始发发射机终端的身份。 分组边界检测系统能够检测网络内所有发射机 - 接收机对的对的分组同步参数。 存储接入系统存储检测到的分组同步参数,并允许接收机访问分组同步参数。 根据本发明的一个实施例,同步方法包括检测同步参数的步骤,并且对于给定的接收机终端,建立用于输入信息分组的始发发射机的身份,访问对应于所识别的发射机的同步参数,调整 接收机基于所访问的同步参数并对输入的信息包进行解码。
    • 88. 发明申请
    • RESISTANCE-BASED ETCH DEPTH DETERMINATION FOR SGT TECHNOLOGY
    • 用于SGT技术的基于电阻的蚀刻深度测定
    • US20090166621A1
    • 2009-07-02
    • US12399632
    • 2009-03-06
    • Tiesheng LiYu WangYingying LouAnup Bhalla
    • Tiesheng LiYu WangYingying LouAnup Bhalla
    • H01L23/58
    • H01L22/34H01L22/12H01L22/14H01L2924/0002H01L2924/00
    • A method for determining the depth etch, a method of forming a shielded gate trench (SGT) structure and a semiconductor device wafer are disclosed. A material layer is formed over part of a substrate having a trench. The material fills the trench. A resist mask is placed over a test portion of the material layer thereby defining a test structure that lies underneath the resist mask. The resist mask does not cover the trench. The material is isotropically etched and a signal related to a resistance change of the test structure is measured. A lateral undercut DL of the test structure is determined from the signal and an etch depth DT is determined from DL. The wafer may comprise one or more test structures forming a bridge circuit; one or more metal contacts that electrically connect the test structures through contact holes: and resist layer including over the test structures.
    • 公开了一种用于确定深度蚀刻的方法,形成屏蔽栅沟槽(SGT)结构的方法和半导体器件晶片。 在具有沟槽的衬底的一部分上形成材料层。 材料填充沟槽。 将抗蚀剂掩模放置在材料层的测试部分上,从而限定位于抗蚀剂掩模下方的测试结构。 抗蚀剂掩模不覆盖沟槽。 该材料被各向同性地蚀刻并且测量与测试结构的电阻变化相关的信号。 从信号确定测试结构的横向底切DL,并且从DL确定蚀刻深度DT。 晶片可以包括形成桥接电路的一个或多个测试结构; 通过接触孔将测试结构电连接的一个或多个金属触点和包括在测试结构上的抗蚀剂层。
    • 89. 发明申请
    • Automatically identifying unique language independent keys correlated with appropriate text strings of various locales by key search
    • 通过关键搜索自动识别与各种语言环境的适当文本字符串相关的独特语言独立键
    • US20090030673A1
    • 2009-01-29
    • US11828695
    • 2007-07-26
    • Al ChakraJohn F. SeflerTeppei TsurumiYu WangMorgan Louis Johnson
    • Al ChakraJohn F. SeflerTeppei TsurumiYu WangMorgan Louis Johnson
    • G06F17/20
    • G06F9/454
    • A method, system and computer program product for automatically identifying unique language independent keys. A “key search” is performed which searches for various language independent keys in a properties file associated with a value or text string entered in a first locale. A second locale is suggested to narrow the number of language independent keys displayed in connection with the value entered in the first locale. Upon receiving the value for the second locale, another key search is performed, where this key search is performed on the language independent keys displayed in connection with the first value entered in association with the first locale. A unique language independent key may be identified based on this subsequent key search. By performing key searches and suggesting a second locale to narrow the number of language independent keys, the time in identifying a unique language independent key is reduced and efficiency is improved.
    • 一种用于自动识别独特的独立密钥的方法,系统和计算机程序产品。 执行“键搜索”,其搜索与在第一区域设置中输入的值或文本串相关联的属性文件中的各种与语言无关的键。 建议第二个区域设置来缩小与第一个区域设置中输入的值相关的显示的独立语言密钥的数量。 在接收到第二区域的值时,执行另一个键搜索,其中对与第一语言环境相关联地输入的第一值显示的与语言无关的键执行该键搜索。 可以基于该随后的密钥搜索来识别独特的语言独立密钥。 通过执行关键搜索并建议第二语言环境以缩小语言无关键的数量,减少了识别独特语言的密钥的时间并提高了效率。
    • 90. 发明申请
    • RESISTANCE-BASED ETCH DEPTH DETERMINATION FOR SGT TECHNOLOGY
    • 用于SGT技术的基于电阻的蚀刻深度测定
    • US20080272371A1
    • 2008-11-06
    • US11690581
    • 2007-03-23
    • Tiesheng LiYu WangYingying LouAnup Bhalla
    • Tiesheng LiYu WangYingying LouAnup Bhalla
    • H01L23/58
    • H01L22/34H01L22/12H01L22/14H01L2924/0002H01L2924/00
    • A method for determining the depth etch, a method of forming a shielded gate trench (SGT) structure and a semiconductor device wafer are disclosed. A material layer is formed over part of a substrate having a trench. The material fills the trench. A resist mask is placed over a test portion of the material layer thereby defining a test structure that lies underneath the resist mask. The resist mask does not cover the trench. The material is isotropically etched and a signal related to a resistance change of the test structure is measured. A lateral undercut DL of the test structure is determined from the signal and an etch depth DT is determined from DL. The wafer may comprise one or more test structures forming a bridge circuit; one or more metal contacts that electrically connect the test structures through contact holes: and resist layer including over the test structures.
    • 公开了一种用于确定深度蚀刻的方法,形成屏蔽栅沟槽(SGT)结构的方法和半导体器件晶片。 在具有沟槽的衬底的一部分上形成材料层。 材料填充沟槽。 将抗蚀剂掩模放置在材料层的测试部分上,从而限定位于抗蚀剂掩模下方的测试结构。 抗蚀剂掩模不覆盖沟槽。 该材料被各向同性地蚀刻并且测量与测试结构的电阻变化相关的信号。 根据信号确定测试结构的横向底切D L L,并且从D L确定蚀刻深度D T T。 晶片可以包括形成桥接电路的一个或多个测试结构; 通过接触孔将测试结构电连接的一个或多个金属触点和包括在测试结构上的抗蚀剂层。