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81. 发明授权

US07879666B2 Semiconductor resistor formed in metal gate stack 有权
标题翻译：半导体电阻器形成在金属栅极堆叠中
公开(公告)号：US07879666B2
公开(公告)日：2011-02-01
申请号：US12177986
申请日：2008-07-23
申请人： Da Zhang , Chendong Zhu , Xiangdong Chen , Melanie Sherony
发明人： Da Zhang , Chendong Zhu , Xiangdong Chen , Melanie Sherony
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L27/0629 , H01L28/20
摘要： A semiconductor process and apparatus fabricate a metal gate electrode (30) and an integrated semiconductor resistor (32) by forming a metal-based layer (26) and semiconductor layer (28) over a gate dielectric layer (24) and then selectively implanting the resistor semiconductor layer (28) in a resistor area (97) to create a conductive upper region (46) and a conduction barrier (47), thereby confining current flow in the resistor semiconductor layer (36) to only the top region (46) in the finally formed device.
摘要翻译：一种半导体工艺和装置，通过在栅极介电层（24）上形成金属基层（26）和半导体层（28），然后选择性地植入金属栅电极（30）和集成半导体电阻器（32）电阻器区域（97）中的电阻器半导体层（28），以产生导电上部区域（46）和导电屏障（47），从而将电流流入电阻器半导体层（36）中仅限于顶部区域（46）在最终形成的装置。

82. 发明申请

US20080206940A1 FORMING A SEMICONDUCTOR DEVICE HAVING EPITAXIALLY GROWN SOURCE AND DRAIN REGIONS 有权
标题翻译：形成具有外源性源和漏区的半导体器件
公开(公告)号：US20080206940A1
公开(公告)日：2008-08-28
申请号：US11680219
申请日：2007-02-28
申请人： Laegu Kang , Vishal P. Trivedi , Da Zhang
发明人： Laegu Kang , Vishal P. Trivedi , Da Zhang
IPC分类号： H01L21/8234
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/84 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/66772
摘要： A semiconductor device structure is made on a semiconductor substrate having a semiconductor layer having isolation regions. A first gate structure is formed over a first region of the semiconductor layer, and a second gate structure is over a second region of the semiconductor layer. A first insulating layer is formed over the first and second regions. The first insulating layer can function as a mask during an etch of the semiconductor layer and can be removed selective to the isolation regions and the sidewall spacers. The first insulating layer is removed from over the first region to leave a remaining portion of the first insulating layer over the second region. The semiconductor layer is recessed in the first region adjacent to the first gate to form recesses. A semiconductor material is epitaxially grown in the recesses. The remaining portion of the first insulating layer is removed.
摘要翻译：在具有具有隔离区域的半导体层的半导体衬底上制造半导体器件结构。第一栅极结构形成在半导体层的第一区域上，第二栅极结构在半导体层的第二区域之上。在第一和第二区域上形成第一绝缘层。第一绝缘层可以在半导体层的蚀刻期间用作掩模，并且可以选择性地去除隔离区域和侧壁间隔物。从第一区域上去除第一绝缘层，以在第二区域上留下第一绝缘层的剩余部分。半导体层凹入与第一栅极相邻的第一区域中以形成凹陷。在凹部中外延生长半导体材料。去除第一绝缘层的剩余部分。

83. 发明申请

US20070210314A1 Semiconductor device with stressors and method therefor 有权
标题翻译：具有应力的半导体器件及其方法
公开(公告)号：US20070210314A1
公开(公告)日：2007-09-13
申请号：US11373536
申请日：2006-03-10
申请人： Brian Winstead , Ted White , Da Zhang
发明人： Brian Winstead , Ted White , Da Zhang
IPC分类号： H01L29/76
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A method for forming a semiconductor device includes providing a substrate region having a first material and a second material overlying the first material, wherein the first material has a different lattice constant from a lattice constant of the second material. The method further includes etching a first opening on a first side of a gate and etching a second opening on a second side of the gate. The method further includes creating a first in-situ p-type doped epitaxial region in the first opening and the second opening, wherein the first in-situ doped epitaxial region is created using the second material. The method further includes creating a second in-situ n-type doped expitaxial region overlying the first in-situ p-type doped epitaxial region in the first opening and the second opening, wherein the second in-situ n-type doped epitaxial region is created using the second material.
摘要翻译：一种形成半导体器件的方法包括提供具有第一材料和覆盖第一材料的第二材料的衬底区域，其中第一材料具有与第二材料的晶格常数不同的晶格常数。该方法还包括蚀刻栅极的第一侧上的第一开口并蚀刻栅极的第二侧上的第二开口。该方法还包括在第一开口和第二开口中产生第一原位p型掺杂外延区域，其中使用第二材料产生第一原位掺杂外延区域。该方法还包括在第一开口和第二开口中形成覆盖第一原位p型掺杂外延区域的第二原位n型掺杂截留区域，其中第二原位n型掺杂外延区域是使用第二种材料创建。

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