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81. 发明授权

US09090864B2 Multi-tube biofilter system for treating waste gas 有权
标题翻译：用于处理废气的多管生物过滤系统
公开(公告)号：US09090864B2
公开(公告)日：2015-07-28
申请号：US13814240
申请日：2011-07-27
申请人： Chunping Yang , Haining Yang , Hong Chen , Guanlong Yu , Guangming Zeng , Shenglian Luo
发明人： Chunping Yang , Haining Yang , Hong Chen , Guanlong Yu , Guangming Zeng , Shenglian Luo
IPC分类号： C12M1/00 , C12M1/12 , B01D53/85
CPC分类号： C12M25/14 , B01D53/85 , B01D2257/708 , Y02A50/2359
摘要： Disclosed is a multi-tube biofilter system for treating waste gas. The multi-tube biofilter system includes a multi-tube biofilter and a nutrient solution supply system. The multi-tube biofilter includes an outer casing, at least two reticulated tubes disposed in the outer casing, a packing medium portion, and a nutrient solution spraying system. The outer casing is opened to define a gas inlet, a gas outlet, and a water outlet therein. The packing medium portion is attached to an outer surface of each of the reticulated tubes, wherein a liquid entering end of the nutrient solution spraying system is in communication with the nutrient solution supply system via a pipeline, and solution spraying ends of the nutrient solution spraying system face the reticulated tubes.
摘要翻译：公开了一种用于处理废气的多管生物滤池系统。多管生物滤池系统包括多管生物过滤器和营养液供应系统。多管生物过滤器包括外壳，设置在外壳中的至少两个网状管，填充介质部分和营养液喷洒系统。外壳打开以在其中限定气体入口，气体出口和出水口。包装介质部分附接到每个网状管的外表面，其中进入营养液喷射系统的一端的液体通过管道与营养液供应系统连通，并且喷洒营养液的溶液喷洒系统面对网状管。

82. 发明授权

US08497168B2 Structure and method to enhance both NFET and PFET performance using different kinds of stressed layers 失效
标题翻译：使用不同种类的应力层来增强NFET和PFET性能的结构和方法
公开(公告)号：US08497168B2
公开(公告)日：2013-07-30
申请号：US13071940
申请日：2011-03-25
申请人： Bruce B. Doris , Haining Yang , Huilong Zhu
发明人： Bruce B. Doris , Haining Yang , Huilong Zhu
IPC分类号： H01L21/335 , H01L21/8232
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823828 , H01L21/823864 , H01L29/6653 , H01L29/7843
摘要： In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nMOS and pMOS transistors), carrier mobility is enhanced or otherwise regulated through the use of layering various stressed films over either the nMOS or pMOS transistor (or both), depending on the properties of the layer and isolating stressed layers from each other and other structures with an additional layer in a selected location. Thus both types of transistors on a single chip or substrate can achieve an enhanced carrier mobility, thereby improving the performance of CMOS devices and integrated circuits.
摘要翻译：在制造互补的金属氧化物半导体（CMOS）场效应晶体管（包括nMOS和pMOS晶体管）的情况下，通过使用在nMOS或pMOS晶体管（或两者）上分层各种应力薄膜来增强或调节载流子迁移率，取决于层的性质并且将应力层彼此隔离并且在所选位置具有附加层的其它结构。因此，单个芯片或衬底上的两种类型的晶体管可以实现增强的载流子迁移率，从而提高CMOS器件和集成电路的性能。

83. 发明授权

US08476674B2 Gate conductor with a diffusion barrier 有权
标题翻译：具有扩散阻挡层的栅极导体
公开(公告)号：US08476674B2
公开(公告)日：2013-07-02
申请号：US13010009
申请日：2011-01-20
申请人： Wai-Kin Li , Haining Yang
发明人： Wai-Kin Li , Haining Yang
IPC分类号： H01L29/66 , H01L27/118
CPC分类号： H01L21/76841 , H01L21/823842 , H01L21/823871 , H01L22/12 , H01L23/58 , H01L29/42376 , H01L29/4238 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： A gate conductor structure is provided having a barrier region between a N-type device and a P-type device, wherein the barrier region minimizes or eliminates cross-diffusion of dopant species across the barrier region. The barrier region comprises at least one sublithographic gap in the gate conductor structure. The sublithographic gap is formed by using self-assembling copolymers to form a sublithographic patterned mask over the gate conductor structure. According to one embodiment, at least one sublithographic gap is a slit or line that traverses the width of the gate conductor structure. The sublithographic gap is sufficiently deep to minimize or prevent cross-diffusion of the implanted dopant from the upper portion of the gate conductor. According to another embodiment, the sublithographic gaps are of sufficient density that cross-diffusion of dopants is reduced or eliminated during an activation anneal such that changes in Vt are minimized.
摘要翻译：提供了具有在N型器件和P型器件之间的势垒区域的栅极导体结构，其中所述势垒区域最小化或消除了所述阻挡区域上的掺杂剂物质的交叉扩散。阻挡区域包括栅极导体结构中的至少一个亚光刻间隙。通过使用自组装共聚物在栅极导体结构上形成亚光刻图案掩模来形成亚光刻间隙。根据一个实施例，至少一个亚光刻间隙是穿过栅极导体结构的宽度的狭缝或线。亚光刻间隙足够深以使注入的掺杂剂从栅极导体的上部最小化或防止交叉扩散。根据另一个实施例，亚光刻间隙具有足够的密度，使得在激活退火期间掺杂剂的交叉扩散减少或消除，使得Vt的变化最小化。

84. 发明授权

US08008724B2 Structure and method to enhance both nFET and pFET performance using different kinds of stressed layers 有权
标题翻译：使用不同种类的应力层来增强nFET和pFET性能的结构和方法
公开(公告)号：US08008724B2
公开(公告)日：2011-08-30
申请号：US10695748
申请日：2003-10-30
申请人： Bruce B. Doris , Haining Yang , Huilong Zhu
发明人： Bruce B. Doris , Haining Yang , Huilong Zhu
IPC分类号： H01L23/62
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823828 , H01L21/823864 , H01L29/6653 , H01L29/7843
摘要： In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nMOS and pMOS transistors), carrier mobility is enhanced or otherwise regulated through the use of layering various stressed films over either the nMOS or pMOS transistor (or both), depending on the properties of the layer and isolating stressed layers from each other and other structures with an additional layer in a selected location. Thus both types of transistors on a single chip or substrate can achieve an enhanced carrier mobility, thereby improving the performance of CMOS devices and integrated circuits.
摘要翻译：在制造互补的金属氧化物半导体（CMOS）场效应晶体管（包括nMOS和pMOS晶体管）的情况下，通过使用在nMOS或pMOS晶体管（或两者）上分层各种应力薄膜来增强或调节载流子迁移率，取决于层的性质并且将应力层彼此隔离并且在所选位置具有附加层的其它结构。因此，单个芯片或衬底上的两种类型的晶体管可以实现增强的载流子迁移率，从而提高CMOS器件和集成电路的性能。

85. 发明申请

US20110140288A1 Systems and Methods Employing a Physically Asymmetric Semiconductor Device Having Symmetrical Electrical Behavior 有权
标题翻译：采用具有对称电气行为的物理不对称半导体器件的系统和方法
公开(公告)号：US20110140288A1
公开(公告)日：2011-06-16
申请号：US12638557
申请日：2009-12-15
申请人： Haining Yang , Chock H. Gan , Zhongze Wang , Beom-Mo Han
发明人： Haining Yang , Chock H. Gan , Zhongze Wang , Beom-Mo Han
IPC分类号： H01L23/50 , H01L21/3205
CPC分类号： H01L27/0207 , H01L21/823425 , H01L21/823475 , H01L27/088 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit device comprising a first elongate structure and a second elongate structure arranged parallel to each other and defining a space therebetween. The integrated circuit device also includes conductive structures distributed in the space between the first and second elongate structures. At least a first one of the conductive structures is placed closer to the first elongate structure than to the second elongate structure. At least a second one of the conductive structures is placed closer to the second elongate structure than to the first elongate structure.
摘要翻译：一种集成电路装置，包括彼此平行布置并且在它们之间限定空间的第一细长结构和第二细长结构。集成电路装置还包括分布在第一和第二细长结构之间的空间中的导电结构。导电结构中的至少第一个被放置成比第二细长结构更靠近第一细长结构。导电结构中的至少第二个被放置成比第一细长结构更靠近第二细长结构。

86. 发明授权

US07816219B2 Field effect transistors (FETs) with multiple and/or staircase silicide 有权
标题翻译：具有多个和/或阶梯硅化物的场效应晶体管（FET）
公开(公告)号：US07816219B2
公开(公告)日：2010-10-19
申请号：US11850076
申请日：2007-09-05
申请人： Xiangdong Chen , Sunfei Fang , Zhijiong Luo , Haining Yang , Huilong Zhu
发明人： Xiangdong Chen , Sunfei Fang , Zhijiong Luo , Haining Yang , Huilong Zhu
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , H01L29/665 , H01L29/6659
摘要： A semiconductor structure and method for forming the same. First, a semiconductor structure is provided, including (a) a semiconductor layer including (i) a channel region and (ii) first and second source/drain (S/D) extension regions, and (iii) first and second S/D regions, (b) a gate dielectric region in direction physical contact with the channel region via a first interfacing surface that defines a reference direction essentially perpendicular to the first interfacing surface, and (c) a gate region in direct physical contact with the gate dielectric region, wherein the gate dielectric region is sandwiched between and electrically insulates the gate region and the channel region. Then, (i) a first shallow contact region is formed in direct physical contact with the first S/D extension region, and (ii) a first deep contact region is formed in direct physical contact with the first S/D region and the first shallow contact region.
摘要翻译：一种半导体结构及其形成方法。首先，提供半导体结构，其包括（a）包括（i）沟道区和（ii）第一和第二源/漏（S / D）延伸区的半导体层，以及（iii）第一和第二S / D 区域，（b）通过限定基本上垂直于第一接口表面的参考方向的第一接口表面方向与沟道区域物理接触的栅极电介质区域，以及（c）与栅极电介质直接物理接触的栅极区域区域，其中栅极电介质区域夹在栅极区域和沟道区域之间并使电绝缘。然后，（i）第一浅接触区域形成为与第一S / D延伸区域直接物理接触，并且（ii）第一深接触区域形成为与第一S / D区域和第一浅/ 浅接触区域。

87. 发明授权

US07790540B2 Structure and method to use low k stress liner to reduce parasitic capacitance 失效
标题翻译：使用低k应力衬垫降低寄生电容的结构和方法
公开(公告)号：US07790540B2
公开(公告)日：2010-09-07
申请号：US11467186
申请日：2006-08-25
申请人： Haining Yang , Wai-Kin Li
发明人： Haining Yang , Wai-Kin Li
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823864 , H01L27/092 , H01L29/7843
摘要： A low k stress liner, which replaces conventional stress liners in CMOS devices, is provided. In one embodiment, a compressive, low k stress liner is provided which can improve the hole mobility in pFET devices. UV exposure of this compressive, low k material results in changing the polarity of the low k stress liner from compressive to tensile. The use of such a tensile, low k stress liner improves electron mobility in nFET devices.
摘要翻译：提供了一种代替CMOS器件中常规应力衬垫的低k应力衬垫。在一个实施例中，提供压缩的低k应力衬垫，其可以改善pFET器件中的空穴迁移率。这种压缩低k材料的紫外线暴露导致低k应力衬垫的极性从压缩变为拉伸。使用这种拉伸的低k应力衬垫提高nFET器件中的电子迁移率。

88. 发明授权

US07737014B2 Reduction of boron diffusivity in pFETs 失效
标题翻译：降低pFET中的硼扩散率
公开(公告)号：US07737014B2
公开(公告)日：2010-06-15
申请号：US10596249
申请日：2003-12-08
申请人： Frederick William Buehrer , Dureseti Chidambarrao , Bruce B. Doris , Hsiang-Jen Huang , Haining Yang
发明人： Frederick William Buehrer , Dureseti Chidambarrao , Bruce B. Doris , Hsiang-Jen Huang , Haining Yang
IPC分类号： H01L21/22 , H01L21/38
CPC分类号： H01L29/7842 , H01L21/22 , H01L21/26513 , H01L21/26586 , H01L21/324 , H01L21/823807 , H01L21/823814 , H01L29/1083 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7843
摘要： A stressed film applied across a boundary defined by a structure or a body (e.g. substrate or layer) of semiconductor material provides a change from tensile to compressive stress in the semiconductor material proximate to the boundary and is used to modify boron diffusion rate during annealing and thus modify final boron concentrations. In the case of a field effect transistor, the gate structure may be formed with or without sidewalls to regulate the location of the boundary relative to source/drain, extension and/or halo implants. Different boron diffusion rates can be produced in the lateral and vertical directions and diffusion rates comparable to arsenic can be achieved. Reduction of junction capacitance of both nFETs and pFETs can be achieved simultaneously with the same process steps.
摘要翻译：应用于由半导体材料的结构或主体（例如衬底或层）限定的边界处的应力膜提供了靠近边界的半导体材料中的拉应力和压缩应力的变化，并用于在退火过程中修饰硼扩散速率，从而改变最终的硼浓度。在场效应晶体管的情况下，栅极结构可以形成有或不具有侧壁以调节边界相对于源极/漏极，延伸和/或晕轮植入物的位置。可以在横向和垂直方向上产生不同的硼扩散速率，并且可以实现与砷相当的扩散速率。可以通过相同的工艺步骤同时实现nFET和pFET的结电容的减小。

89. 发明授权

US07732270B2 Device having enhanced stress state and related methods 有权
标题翻译：具有增强的应力状态和相关方法的装置
公开(公告)号：US07732270B2
公开(公告)日：2010-06-08
申请号：US11972964
申请日：2008-01-11
申请人： Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha , Haining Yang , Huilong Zhu
发明人： Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha , Haining Yang , Huilong Zhu
IPC分类号： H01L21/8238
CPC分类号： H01L29/7843 , H01L21/823807 , H01L29/66772 , Y10S438/938
摘要： The present invention provides a semiconductor device having dual nitride liners, which provide an increased transverse stress state for at least one FET and methods for the manufacture of such a device. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner to the device and applying a second silicon nitride liner adjacent the first silicon nitride liner, wherein at least one of the first and second silicon nitride liners induces a transverse stress in a silicon channel beneath at least one of the first and second silicon nitride liner.
摘要翻译：本发明提供一种具有双重氮化物衬垫的半导体器件，其为至少一个FET提供增加的横向应力状态以及用于制造这种器件的方法。本发明的第一方面提供了一种用于制造半导体器件的方法，包括以下步骤：将第一氮化硅衬垫施加到器件上并施加与第一氮化硅衬垫相邻的第二氮化硅衬垫，其中至少一个第一和第二氮化硅衬垫在第一和第二氮化硅衬里中的至少一个之下的硅沟道中引起横向应力。

90. 发明授权

US07678658B2 Structure and method for improved SRAM interconnect 有权
标题翻译：用于改进SRAM互连的结构和方法
公开(公告)号：US07678658B2
公开(公告)日：2010-03-16
申请号：US12018440
申请日：2008-01-23
申请人： Haining Yang , Robert C. Wong
发明人： Haining Yang , Robert C. Wong
IPC分类号： H01L21/20
CPC分类号： H01L27/1104 , H01L21/84 , H01L27/0207 , H01L27/11 , H01L27/1203
摘要： A method of forming an improved static random access memory (SRAM) interconnect structure is provided. The method includes forming a sidewall spacer around a periphery of a patterned poly-silicon layer formed over a silicon layer of a semiconductor substrate; removing the patterned poly-silicon layer for exposing a portion of a cap layer; etching the exposed portion of the cap layer for revealing a portion of the silicon layer; etching the portion of the silicon layer, in which a portion of said silicon layer connects at least a portion of pull-down device of said SRAM to at least a portion of pull-up device of said SRAM; forming a gate oxide; and forming a gate conductor over the gate oxide. An interconnect structure is also provided.
摘要翻译：提供了形成改进的静态随机存取存储器（SRAM）互连结构的方法。该方法包括在形成在半导体衬底的硅层上的图案化多晶硅层的周围形成侧壁隔离物; 去除图案化的多晶硅层以暴露盖层的一部分; 蚀刻盖层的暴露部分以露出硅层的一部分; 蚀刻硅层的部分，其中所述硅层的一部分将所述SRAM的下拉器件的至少一部分连接到所述SRAM的上拉器件的至少一部分; 形成栅极氧化物; 以及在所述栅极氧化物上形成栅极导体。还提供互连结构。

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