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81. 发明授权

US07871922B2 Methods for forming interconnect structures that include forming air gaps between conductive structures 有权
标题翻译：形成互连结构的方法，其包括在导电结构之间形成气隙
公开(公告)号：US07871922B2
公开(公告)日：2011-01-18
申请号：US11733556
申请日：2007-04-10
申请人： Chung-Shi Liu , Chen-Hua Yu
发明人： Chung-Shi Liu , Chen-Hua Yu
IPC分类号： H01L21/4763
CPC分类号： H01L21/7682 , H01L21/76825 , H01L21/76826 , H01L21/76831 , H01L21/76832 , H01L21/76849 , H01L21/76867
摘要： A method for forming a semiconductor structure includes forming a sacrificial layer over a substrate. A first dielectric layer is formed over the sacrificial layer. A plurality of conductive structures are formed within the sacrificial layer and the first dielectric layer. The sacrificial layer is treated through the first dielectric layer, at least partially removing the sacrificial layer and forming at least one air gap between two of the conductive structures. A surface of the first dielectric layer is treated, forming a second dielectric layer over the first dielectric layer, after the formation of the air gap. A third dielectric layer is formed over the second dielectric layer. At least one opening is formed within the third dielectric layer such that the second dielectric layer substantially protects the first dielectric layer from damage by the step of forming the opening.
摘要翻译：一种用于形成半导体结构的方法包括在衬底上形成牺牲层。在牺牲层上形成第一介电层。在牺牲层和第一介电层内形成多个导电结构。牺牲层通过第一介电层进行处理，至少部分去除牺牲层并在两个导电结构之间形成至少一个气隙。处理第一电介质层的表面，在形成气隙之后在第一介电层上形成第二电介质层。在第二电介质层上形成第三电介质层。至少一个开口形成在第三电介质层内，使得第二电介质层基本上保护第一电介质层不受形成开口的步骤的损害。

82. 发明申请

US20110003474A1 Germanium-Containing Dielectric Barrier for Low-K Process 有权
标题翻译：含锗的介质阻挡层用于低K工艺
公开(公告)号：US20110003474A1
公开(公告)日：2011-01-06
申请号：US12881939
申请日：2010-09-14
申请人： Chung-Shi Liu , Chen-Hua Yu
发明人： Chung-Shi Liu , Chen-Hua Yu
IPC分类号： H01L21/768
CPC分类号： H01L23/53295 , H01L21/76834 , H01L21/76835 , H01L21/76849 , H01L21/76856 , H01L21/76867 , H01L21/76886 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure and methods of forming the same are provided. The semiconductor structure includes a semiconductor substrate; a first dielectric layer over the semiconductor substrate; a conductive wiring in the first dielectric layer; and a copper germanide nitride layer over the conductive wiring.
摘要翻译：提供半导体结构及其形成方法。半导体结构包括半导体衬底; 半导体衬底上的第一电介质层; 第一电介质层中的导电布线; 以及导电布线上的锗锗化锗氮化物层。

83. 发明授权

US07858519B2 Integrated circuit and manufacturing method of copper germanide and copper silicide as copper capping layer 有权
标题翻译：锗锗和铜硅化铜作为铜覆盖层的集成电路和制造方法
公开(公告)号：US07858519B2
公开(公告)日：2010-12-28
申请号：US12264095
申请日：2008-11-03
申请人： Chung-Shi Liu , Chen-Hua Yu
发明人： Chung-Shi Liu , Chen-Hua Yu
IPC分类号： H01L21/44
CPC分类号： H01L21/76849 , H01L21/76846 , H01L21/76856 , H01L21/76867 , H01L21/76886 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method is provided for forming a capping layer comprising Cu, N, and also Si and/or Ge onto a copper conductive structure, said method comprising the sequential steps of: forming, at a temperature range between 200° C. up to 400° C., at least one capping layer onto said copper conductive structure by exposing said structure to a GeH4 and/or a SiH4 comprising ambient, performing a NH3 plasma treatment thereby forming an at least partly nitrided capping layer, forming a dielectric barrier layer onto said at least partly nitrided capping layer, wherein prior to said step of forming said at least one capping layer a pre-annealing step of said copper conductive structure is performed at a temperature range between 250° C. up to 450° C.
摘要翻译：提供了一种用于在铜导电结构上形成包含Cu，N以及Si和/或Ge的覆盖层的方法，所述方法包括以下顺序步骤：在200℃至400℃的温度范围内通过将所述结构暴露于包含环境的GeH 4和/或SiH 4，执行NH 3等离子体处理从而形成至少部分氮化的覆盖层，在所述铜导电结构上至少一个覆盖层，在所述铜导电结构上形成介电阻挡层至少部分氮化的覆盖层，其中在形成所述至少一个覆盖层的所述步骤之前，所述铜导电结构的预退火步骤在250℃至450℃的温度范围内进行。

84. 发明授权

US07799628B2 Advanced metal gate method and device 有权
标题翻译：先进的金属门法和器件
公开(公告)号：US07799628B2
公开(公告)日：2010-09-21
申请号：US12354558
申请日：2009-01-15
申请人： Chung-Shi Liu , Hsiang-Yi Wang , Cheng-Tung Lin , Chen-Hua Yu
发明人： Chung-Shi Liu , Hsiang-Yi Wang , Cheng-Tung Lin , Chen-Hua Yu
IPC分类号： H01L21/8238
CPC分类号： H01L21/28088 , H01L21/265 , H01L21/823835 , H01L21/823842 , H01L29/4966 , H01L29/51 , H01L29/78
摘要： The present disclosure provides a method of fabricating a semiconductor device that includes forming a high-k dielectric over a substrate, forming a first metal layer over the high-k dielectric, forming a second metal layer over the first metal layer, forming a first silicon layer over the second metal layer, implanting a plurality of ions into the first silicon layer and the second metal layer overlying a first region of the substrate, forming a second silicon layer over the first silicon layer, patterning a first gate structure over the first region and a second gate structure over a second region, performing an annealing process that causes the second metal layer to react with the first silicon layer to form a silicide layer in the first and second gate structures, respectively, and driving the ions toward an interface of the first metal layer and the high-k dielectric in the first gate structure.
摘要翻译：本公开提供一种制造半导体器件的方法，其包括在衬底上形成高k电介质，在高k电介质上形成第一金属层，在第一金属层上形成第二金属层，形成第一硅在所述第二金属层上方，将多个离子注入到所述第一硅层中，并且所述第二金属层覆盖在所述基板的第一区域上，在所述第一硅层上形成第二硅层，在所述第一区上形成第一栅极结构以及在第二区域上的第二栅极结构，执行使所述第二金属层与所述第一硅层反应以在所述第一和第二栅极结构中分别形成硅化物层的退火处理，并将所述离子驱动到第一栅极结构中的第一金属层和高k电介质。

85. 发明申请

US20100207177A1 METHOD FOR PRODUCING A COPPER CONTACT 审中-公开
标题翻译：生产铜接触方法
公开(公告)号：US20100207177A1
公开(公告)日：2010-08-19
申请号：US12641945
申请日：2009-12-18
申请人： Chung-Shi Liu , Gerald Beyer , Steven Demuynck , Zsolt Tokei , Roger Palmans , Chao Zhao , Chen-Hua Yu
发明人： Chung-Shi Liu , Gerald Beyer , Steven Demuynck , Zsolt Tokei , Roger Palmans , Chao Zhao , Chen-Hua Yu
IPC分类号： H01L23/532 , H01L21/768 , H01L29/78 , H01L23/522
CPC分类号： H01L21/76843 , H01L21/76831 , H01L21/76855 , H01L21/76856 , H01L21/76864 , H01L21/76873 , H01L23/485 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method for producing a contact through the pre-metal dielectric (PMD) layer of an integrated circuit, between the front end of line and the back end of line, and the device produced thereby are disclosed. The PMD layer includes oxygen. In one aspect, the method includes producing a hole in the PMD, depositing a conductive barrier layer at the bottom of the hole, depositing a CuMn alloy on the bottom and side walls of the hole, filling the remaining portion of the hole with Cu. The method further includes performing an anneal process to form a barrier on the side walls of the hole, wherein the barrier has an oxide including Mn. The method further includes performing a CMP process.
摘要翻译：公开了一种通过集成电路的前金属电介质（PMD）层之间的线的前端和后端之间产生接触的方法以及由此制造的器件。 PMD层包括氧气。一方面，该方法包括在PMD中产生孔，在孔的底部沉积导电阻挡层，在孔的底部和侧壁上沉积CuMn合金，用Cu填充孔的剩余部分。所述方法还包括进行退火处理以在所述孔的侧壁上形成阻挡层，其中所述势垒具有包括Mn的氧化物。该方法还包括执行CMP处理。

86. 发明申请

US20100159693A1 Method of Forming Via Recess in Underlying Conductive Line 审中-公开
标题翻译：在导电线路中通过凹陷形成的方法
公开(公告)号：US20100159693A1
公开(公告)日：2010-06-24
申请号：US12715175
申请日：2010-03-01
申请人： Chung-Shi Liu , Chen-Hua Yu , Horng-Huei Tseng
发明人： Chung-Shi Liu , Chen-Hua Yu , Horng-Huei Tseng
IPC分类号： H01L21/768
CPC分类号： H01L23/5329 , H01L21/76802 , H01L21/76805 , H01L21/76807 , H01L21/76816 , H01L21/76834 , H01L21/76844 , H01L21/76847 , H01L23/5226 , H01L23/53214 , H01L23/53228 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a semiconductor device includes forming a via in a dielectric layer that opens to a conductive line underlying the dielectric layer, and forming a via recess in the conductive line at the via. The via recess in the conductive line has a depth ranging from about 100 angstroms to about 600 angstroms. Via-fill material fills the via recess and at least partially fills the via, such that the via-fill material is electrically connected to the conductive line. The via recess may have a same size or smaller cross-section area than that of the via, for example. Such via structure may be part of a dual damascene structure in an intermetal dielectric structure, for example.
摘要翻译：制造半导体器件的方法包括在介电层下方形成导电线的电介质层中形成通孔，以及在通孔的导电线中形成通路凹槽。导线中的通路凹槽的深度范围为约100埃至约600埃。通孔填充材料填充通孔凹部并且至少部分地填充通孔，使得通孔填充材料电连接到导电线。例如，通孔凹部可以具有与通孔相同的尺寸或更小的横截面面积。例如，这种通孔结构可以是金属间电介质结构中的双镶嵌结构的一部分。

87. 发明申请

US20080185722A1 Formation process of interconnect structures with air-gaps and sidewall spacers 审中-公开
标题翻译：具有气隙和侧壁间隔物的互连结构的形成过程
公开(公告)号：US20080185722A1
公开(公告)日：2008-08-07
申请号：US11702264
申请日：2007-02-05
申请人： Chung-Shi Liu , Chen-Hua Yu , Yuh-Jier Mii , Yuan-Chen Sun
发明人： Chung-Shi Liu , Chen-Hua Yu , Yuh-Jier Mii , Yuan-Chen Sun
IPC分类号： H01L23/528
CPC分类号： H01L21/7682 , H01L21/76831 , H01L21/76849
摘要： An integrated circuit structure having air gaps is provided. The integrated circuit includes a conductive line; a sidewall spacer on a sidewall of the conductive line, wherein the sidewall spacer comprises a dielectric material; an air-gap horizontally adjoining the sidewall spacer; and a dielectric layer on the air-gap.
摘要翻译：提供具有气隙的集成电路结构。集成电路包括导线; 在所述导电线的侧壁上的侧壁间隔件，其中所述侧壁间隔件包括电介质材料; 水平地邻接所述侧壁间隔件的气隙; 和气隙上的介电层。

88. 发明申请

US20070117374A1 Method of forming via recess in underlying conductive line 审中-公开
标题翻译：在下面的导线中形成通孔凹槽的方法
公开(公告)号：US20070117374A1
公开(公告)日：2007-05-24
申请号：US11652210
申请日：2007-01-11
申请人： Chung-Shi Liu , Chen-Hua Yu , Horng-Huei Tseng
发明人： Chung-Shi Liu , Chen-Hua Yu , Horng-Huei Tseng
IPC分类号： H01L21/4763
CPC分类号： H01L23/5329 , H01L21/76802 , H01L21/76805 , H01L21/76807 , H01L21/76816 , H01L21/76834 , H01L21/76844 , H01L21/76847 , H01L23/5226 , H01L23/53214 , H01L23/53228 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a semiconductor device includes forming a via in a dielectric layer that opens to a conductive line underlying the dielectric layer, and forming a via recess in the conductive line at the via. The via recess in the conductive line has a depth ranging from about 100 angstroms to about 600 angstroms. Via-fill material fills the via recess and at least partially fills the via, such that the via-fill material is electrically connected to the conductive line. The via recess may have a same size or smaller cross-section area than that of the via, for example. Such via structure may be part of a dual damascene structure in an intermetal dielectric structure, for example.
摘要翻译：制造半导体器件的方法包括在介电层下方形成导电线的电介质层中形成通孔，以及在通孔中的导电线中形成通路凹槽。导线中的通路凹槽的深度范围为约100埃至约600埃。通孔填充材料填充通孔凹部并且至少部分地填充通孔，使得通孔填充材料电连接到导电线。例如，通孔凹部可以具有与通孔相同的尺寸或更小的横截面面积。例如，这种通孔结构可以是金属间电介质结构中的双镶嵌结构的一部分。

89. 发明授权

US06876082B2 Refractory metal nitride barrier layer with gradient nitrogen concentration 有权
$Refractory metal nitride barrier layer with gradient nitrogen concentration$
公开(公告)号：US06876082B2
公开(公告)日：2005-04-05
申请号：US10214638
申请日：2002-08-08
申请人： Hsien-Ming Lee , Shing-Chuang Pan , Chung-Shi Liu , Chen-Hua Yu
发明人： Hsien-Ming Lee , Shing-Chuang Pan , Chung-Shi Liu , Chen-Hua Yu
IPC分类号： H01L21/285 , H01L21/768 , H01L23/48
CPC分类号： H01L21/76846 , H01L21/2855
摘要： Within a microelectronic fabrication and a method for fabricating the microelectronic fabrication a barrier layer is formed over a substrate. Within the method and the microelectronic fabrication the barrier layer is formed of a refractory metal nitride barrier material having within its thickness a gradient in nitrogen concentration. The barrier layer has low resistivity and improved electromigration performance.

90. 发明授权

US06403465B1 Method to improve copper barrier properties 有权
标题翻译：改善铜屏障性能的方法
公开(公告)号：US06403465B1
公开(公告)日：2002-06-11
申请号：US09473033
申请日：1999-12-28
申请人： Chung-Shi Liu , Chen-Hua Yu
发明人： Chung-Shi Liu , Chen-Hua Yu
IPC分类号： H01L214763
CPC分类号： H01L21/76873 , H01L21/76843 , H01L21/76846
摘要： A method is disclosed to improve copper barrier and adhesion properties of copper interconnections in integrated circuits. It is shown that combining ion metal plasma (IMP) deposition along with in-situ chemical vapor deposition (CVD) of barrier and adhesion materials provides the desired adhesion of and barrier to diffusion of copper in damascene structures. IMP deposition is performed with tantalum or tantalum nitride while CVD deposition is performed with a binary or a ternary compound from a group consisting of titanium nitride, tungsten nitride, tungsten silicon nitride, tantalum silicon nitride, titanium silicon nitride. IMP deposition provides good adhesion of copper to insulator materials, while CVD deposition provides good sidewall coverage in a copper filled trench and a copper seed layer provides good adhesion of bulk copper to adhesion/barrier layer. The IMP/CVD deposited adhesion/barrier layer is thin, thus providing low via resistance.
摘要翻译：公开了一种提高集成电路中铜互连的铜屏障和粘合性能的方法。显示出结合离子金属等离子体（IMP）沉积以及阻挡层和粘合材料的原位化学气相沉积（CVD）提供铜在镶嵌结构中的扩散的期望的粘附和屏障。使用钽或氮化钽进行IMP沉积，同时使用来自氮化钛，氮化钨，氮化硅，氮化钽，氮化钛的二元或三元化合物进行CVD沉积。 IMP沉积提供了铜与绝缘体材料的良好粘附性，而CVD沉积在铜填充的沟槽中提供良好的侧壁覆盖，并且铜籽晶层提供了大块铜对粘附/阻挡层的良好粘附。 IMP / CVD沉积的粘附/阻挡层薄，因此提供低通孔电阻。

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