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81. 发明授权

US07919406B2 Structure and method for forming pillar bump structure having sidewall protection 有权
标题翻译：用于形成具有侧壁保护的支柱凸块结构的结构和方法
公开(公告)号：US07919406B2
公开(公告)日：2011-04-05
申请号：US12791127
申请日：2010-06-01
申请人： Ming Hung Tseng , Young-Chang Lien , Chen-Shien Chen , Chen-Cheng Kuo
发明人： Ming Hung Tseng , Young-Chang Lien , Chen-Shien Chen , Chen-Cheng Kuo
IPC分类号： H01L21/44
CPC分类号： H01L24/11 , H01L24/13 , H01L2224/11462 , H01L2224/11472 , H01L2224/1182 , H01L2224/11849 , H01L2224/11906 , H01L2224/13082 , H01L2224/13111 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13562 , H01L2224/136 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01018 , H01L2924/01022 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/00014 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599
摘要： A method for forming a metal pillar bump structure is provided. In one embodiment, a passivation layer is formed over a semiconductor substrate and a conductive layer is formed over the passivation layer. A patterned and etched photoresist layer is provided above the conductive layer, the photoresist layer defining at least one opening therein. A metal layer is deposited in the at least one opening. Portions of the photoresist layer are etched along one or more interfaces between the photoresist layer and the metal layer to form cavities. A solder material is deposited in the at least one opening, the solder material filling the cavities and a portion of the opening above the metal layer. The remaining photoresist layer and the conductive layer not formed under the copper layer are removed. The solder material is then reflown to encapsulate the metal layer.
摘要翻译：提供一种用于形成金属柱凸块结构的方法。在一个实施例中，在半导体衬底上形成钝化层，并且在钝化层上方形成导电层。在导电层之上设置图案化和蚀刻的光致抗蚀剂层，光致抗蚀剂层在其中限定至少一个开口。金属层沉积在至少一个开口中。光致抗蚀剂层的一部分沿着光致抗蚀剂层和金属层之间的一个或多个界面被蚀刻以形成空腔。焊料材料沉积在至少一个开口中，焊料材料填充空腔和金属层上方的开口的一部分。去除残留的光致抗蚀剂层和未形成在铜层之下的导电层。然后将焊料材料重新包覆以封装金属层。

82. 发明授权

US07888236B2 Semiconductor device and fabrication methods thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US07888236B2
公开(公告)日：2011-02-15
申请号：US11798432
申请日：2007-05-14
申请人： Han-Ping Pu , Bai-Yao Lou , Dean Wang , Ching-Wen Hsiao , Kai-Ming Ching , Chen-Cheng Kuo , Wen-Chih Chiou , Ding-Chung Lu , Shang-Yun Hou
发明人： Han-Ping Pu , Bai-Yao Lou , Dean Wang , Ching-Wen Hsiao , Kai-Ming Ching , Chen-Cheng Kuo , Wen-Chih Chiou , Ding-Chung Lu , Shang-Yun Hou
IPC分类号： H01L21/00
CPC分类号： H01L21/78 , H01L2224/05001 , H01L2224/05022 , H01L2224/05023 , H01L2224/051 , H01L2224/05572 , H01L2224/056 , H01L2224/11 , H01L2924/00014
摘要： A method for packaging a semiconductor device disclosed. A substrate comprising a plurality of dies, separated by scribe line areas respectively is provided, wherein at least one layer is overlying the substrate. A portion of the layer within the scribe lines area is removed by photolithography and etching to form openings. The substrate is sawed along the scribe line areas, passing the openings. In alternative embodiment, a first substrate comprising a plurality of first dies separated by first scribe line areas respectively is provided, wherein at least one first structural layer is overlying the first substrate. The first structural layer is patterned to form first openings within the first scribe line areas. A second substrate comprising a plurality of second dies separated by second scribe line areas respectively is provided, wherein at least one second structural layer is overlying the substrate. The second structural layer is patterned to form second openings within the second scribe line areas. The first substrate and the second substrate are bonded to form a stack structure. The stack structure is cut along the first and second scribe line areas, passing the first and second openings.
摘要翻译：一种封装半导体器件的方法。提供了包括分别由划线区域分隔的多个管芯的衬底，其中至少一层覆盖衬底。通过光刻和蚀刻去除划线部分内的层的一部分以形成开口。沿着划线区域锯切基板，通过开口。在替代实施例中，提供了包括分别由第一划线区域分开的多个第一裸片的第一衬底，其中至少一个第一结构层覆盖在第一衬底上。图案化第一结构层以在第一划线区域内形成第一开口。提供了包括分别由第二划线区域分开的多个第二裸片的第二衬底，其中至少一个第二结构层覆盖在衬底上。图案化第二结构层以在第二划线区域内形成第二开口。第一基板和第二基板被接合以形成堆叠结构。沿着第一和第二划线区域切割堆叠结构，使第一和第二开口通过。

83. 发明申请

US20100090304A1 BONDING PROCESS FOR CMOS IMAGE SENSOR 有权
标题翻译： CMOS图像传感器的结合工艺
公开(公告)号：US20100090304A1
公开(公告)日：2010-04-15
申请号：US12626296
申请日：2009-11-25
申请人： Jen-Cheng Liu , Dun-Nian Yaung , Chen-Cheng Kuo , Chen-Shien Chen , Shou-Gwo Wuu
发明人： Jen-Cheng Liu , Dun-Nian Yaung , Chen-Cheng Kuo , Chen-Shien Chen , Shou-Gwo Wuu
IPC分类号： H01L31/0232 , H01L31/18 , H01L21/60
CPC分类号： H01L21/76898 , H01L23/3171 , H01L23/481 , H01L24/12 , H01L27/14618 , H01L27/14683 , H01L2224/05001 , H01L2224/05009 , H01L2224/05548 , H01L2224/0557 , H01L2924/01019 , H01L2924/01068 , H01L2924/01078 , H01L2924/04941 , H01L2924/12043 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/00
摘要： The present disclosure provides a method of making an integrated circuit (IC). The method includes forming an electric device on a front side of a substrate; forming a top metal pad on the front side of the substrate, the top metal pad being coupled to the electric device; forming a passivation layer on the front side of the substrate, the top metal pad being embedded in the passivation layer; forming an opening in the passivation layer, exposing the top metal pad; forming a deep trench in the substrate; filling a conductive material in the deep trench and the opening, resulting in a though-wafer via (TWV) feature in the deep trench and a pad-TWV feature in the opening, where the top metal pad being connected to the TWV feature through the pad-TWV feature; and applying a polishing process to remove excessive conductive material, forming a substantially planar surface.
摘要翻译：本公开提供了制造集成电路（IC）的方法。该方法包括在基板的正面上形成电子装置; 在所述基板的前侧形成顶部金属焊盘，所述顶部金属焊盘联接到所述电气装置; 在所述基板的正面上形成钝化层，所述顶部金属焊盘嵌入所述钝化层中; 在钝化层中形成开口，暴露顶部金属垫; 在衬底中形成深沟槽; 在深沟槽和开口中填充导电材料，导致深沟槽中的贯穿晶片通孔（TWV）特征和开口中的焊盘TWV特征，其中顶部金属焊盘通过该沟槽连接到TWV特征 pad-TWV功能; 以及施加抛光工艺以去除过量的导电材料，形成基本平坦的表面。

84. 发明授权

US07557423B2 Semiconductor structure with a discontinuous material density for reducing eddy currents 有权
标题翻译：具有不连续材料密度的半导体结构，用于减少涡流
公开(公告)号：US07557423B2
公开(公告)日：2009-07-07
申请号：US11850647
申请日：2007-09-05
申请人： Kai-Ming Ching , Chen Chen-Shien , Han-Hsiang Huang , Chih-Hua Chen , Chen-Cheng Kuo
发明人： Kai-Ming Ching , Chen Chen-Shien , Han-Hsiang Huang , Chih-Hua Chen , Chen-Cheng Kuo
IPC分类号： H01L23/48
CPC分类号： H01L27/08 , H01L23/5227 , H01L28/10 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure includes an inductor; and a semiconductor substrate underlying the inductor, having a discontinuous material density across a plane underneath and in parallel with the inductor, thereby reducing eddy currents induced by an electrical current flowing through the inductor.
摘要翻译：半导体结构包括电感器; 以及位于电感器下方的半导体衬底，其具有在电感器下方并与电感平行的平面上的不连续材料密度，从而减少由流过电感器的电流引起的涡流。

85. 发明申请

US20090134500A1 Structures for Preventing Cross-talk Between Through-Silicon Vias and Integrated Circuits 有权
标题翻译：防止通硅通孔与集成电路之间串扰的结构
公开(公告)号：US20090134500A1
公开(公告)日：2009-05-28
申请号：US11945022
申请日：2007-11-26
申请人： Chen-Cheng Kuo
发明人： Chen-Cheng Kuo
IPC分类号： H01L23/552
CPC分类号： H01L25/0657 , H01L23/481 , H01L23/552 , H01L23/562 , H01L23/585 , H01L23/66 , H01L2223/6688 , H01L2224/16 , H01L2225/06513 , H01L2225/06541
摘要： A semiconductor chip includes a through-silicon via (TSV), a device region, and a cross-talk prevention ring encircling one of the device region and the TSV. The TSV is isolated from substantially all device regions comprising active devices by the cross-talk prevention ring.
摘要翻译：一种半导体芯片包括环形通孔（TSV），器件区域和环绕该器件区域和TSV之一的串扰防止环。 TSV通过串扰防止环从基本上包括有源设备的所有设备区域隔离。

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