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81. 发明授权

US5760728A Input stage for an analog-to-digital converter and method of operation thereof 失效
标题翻译：模数转换器的输入级及其操作方法
公开(公告)号：US5760728A
公开(公告)日：1998-06-02
申请号：US794622
申请日：1997-02-03
申请人： Michael R. May , John E. Willis
发明人： Michael R. May , John E. Willis
IPC分类号： H03M3/02 , H03M1/00
CPC分类号： H03M3/344 , H03M3/458
摘要： An input stage (200) for use in a Sigma-Delta analog-to-digital converter (300) that utilizes a frequency independent impedance (202) in parallel with a frequency dependent impedance (210, 212). An analog input signal (Vin) is concurrently passed through both impedances to a terminal of an operational amplifier (208). A feedback reference (REF) from the A/D converter (316) is also coupled to the terminal of the op amp (208) via a second frequency independent impedance (204). The frequency dependent impedance (210, 212) enables amplification of the input signal at higher frequencies to boost signal-to-noise ratio at such frequencies. Thus, the frequency dependent impedance significantly improves signal-to-noise ratio in the Sigma-Delta converter, thereby avoiding any pre-filtering of the Sigma-Delta inputs.
摘要翻译：一种用于Σ-Δ模数转换器（300）的输入级（200），其利用与频率相关阻抗（210,212）并联的频率无关阻抗（202）。模拟输入信号（Vin）同时通过两个阻抗到运算放大器（208）的端子。来自A / D转换器（316）的反馈参考（REF）也经由第二频率独立阻抗（204）耦合到运算放大器（208）的端子。频率相关阻抗（210,212）能够以较高频率对输入信号进行放大，以提高这些频率下的信噪比。因此，频率相关阻抗显着提高了Sigma-Delta转换器中的信噪比，从而避免了Sigma-Delta输入的任何预滤波。

82. 发明授权

US5729166A Digitally implemented frequency multiplication circuit having adjustable multiplication ratio and method of operation 失效
标题翻译：数字实现的倍增电路具有可调倍增比和操作方法
公开(公告)号：US5729166A
公开(公告)日：1998-03-17
申请号：US660779
申请日：1996-06-10
申请人： Michael R. May , Michael D. Cave
发明人： Michael R. May , Michael D. Cave
IPC分类号： H03K5/00 , H03K3/72
CPC分类号： H03K5/00006
摘要： A frequency multiplication circuit (10) includes a periodic interval selector (12) and a delay element (28) to produce an output signal (26) in phase with, and at a frequency multiple of a reference signal (18). During a first time interval, the periodic interval selector (12) bases the output signal (26) on the reference signal (18). During a second time interval, the periodic interval selector (12) bases the output signal (26) on a delayed signal (22) produced by the delay element (14) based upon the output signal (26). Feedback from the output of the periodic interval selector (12) through the delay element (14) and the operation of the periodic interval selector (12) causes the output signal (26) to be in phase with, and at a frequency multiple of the reference signal (18). Delay adjuster (52) adjusts delay produced by the delay element (14) to adjust the output signal (26) to cause the output signal (26) to have a desired duty cycle consistency. Periodic interval selector (12) and delay adjuster (52) may be adjusted as well as to adjust a frequency multiplication ratio of the frequency multiplication circuit (10). Delay element (14) may be implemented with digital circuit elements such as inverters, other logic gates, or individual circuit elements operably coupled to produce a controllable variable delay.
摘要翻译：倍频电路（10）包括周期性间隔选择器（12）和延迟元件（28），以产生与参考信号（18）同相和频率倍数的输出信号（26）。在第一时间间隔期间，周期性间隔选择器（12）将输出信号（26）基于参考信号（18）。在第二时间间隔期间，周期间隔选择器（12）基于输出信号（26）将输出信号（26）基于由延迟元件（14）产生的延迟信号（22）。来自周期性间隔选择器（12）的输出到延迟元件（14）的反馈和周期性间隔选择器（12）的操作使得输出信号（26）与参考信号（18）。延迟调整器（52）调整由延迟元件（14）产生的延迟以调整输出信号（26），使得输出信号（26）具有期望的占空比一致性。可以调节周期性间隔选择器（12）和延迟调节器（52）以及调节倍频电路（10）的倍频比。延迟元件（14）可以用诸如逆变器，其它逻辑门或可操作地耦合以产生可控可变延迟的单独电路元件的数字电路元件来实现。

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