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81. 发明授权

US07251167B2 Method for programming multi-level nitride read-only memory cells 有权
标题翻译：多级氮化物只读存储单元的编程方法
公开(公告)号：US07251167B2
公开(公告)日：2007-07-31
申请号：US11026947
申请日：2004-12-29
申请人： Hsiang-Lan Lung , Chao-I Wu
发明人： Hsiang-Lan Lung , Chao-I Wu
IPC分类号： G11C16/04
CPC分类号： H01L29/7923
摘要： A method of programming data regions in a nitride read-only memory cell is described. In an erased state, the nitride read-only memory cell exhibits a low Vt value. A data region that is to be programmed to a highest Vt value is programmed first. Remaining data regions in the nitride read-only memory cell are programmed in a time order according to their descending Vt values. For a nitride read-only memory cell that, in an erased state, exhibits a high Vt value, a data region that is to be programmed to a lowest Vt value is programmed first with remaining data regions programmed in a time order according to their ascending Vt values.
摘要翻译：描述了在氮化物只读存储器单元中编程数据区域的方法。在擦除状态下，氮化物只读存储器单元呈现低V值。首先编程要编程到最高V SUB值的数据区。氮化物只读存储器单元中的剩余数据区域按照其下降的V t值的时间顺序被编程。对于在擦除状态下呈现高V V值的氮化物只读存储器单元，要编程到最低V OUT值的数据区域首先编程其余数据区域按照时间顺序按照它们的升序值编程。

82. 发明申请

US20070158645A1 Self-align planerized bottom electrode phase change memory and manufacturing method 有权
标题翻译：自对准平面化底电极相变记忆及制造方法
公开(公告)号：US20070158645A1
公开(公告)日：2007-07-12
申请号：US11351296
申请日：2006-02-09
申请人： Hsiang-Lan Lung
发明人： Hsiang-Lan Lung
IPC分类号： H01L29/08
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/1233 , H01L45/1246 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1691
摘要： A method is described for self-aligning a bottom electrode in a phase change random access memory PCRAM device where a top electrode serves as a mask for self-aligning etching of the bottom electrode. The bottom electrode has a top surface that is planarized by chemical mechanical polishing. The top electrode also has a top surface that is planarized by chemical mechanical polishing. A bottom electrode layer like TiN is formed over a substrate and prior to the formation of a via during subsequent process steps. A first dielectric layer is formed over the bottom electrode layer, and a second dielectric layer is formed over the first dielectric layer. A via is formed at a selected section that extends through the first and second dielectric layers.
摘要翻译：描述了一种用于在相变随机存取存储器PCRAM器件中自对准底部电极的方法，其中顶部电极用作底部电极的自对准蚀刻的掩模。底部电极具有通过化学机械抛光而平坦化的顶表面。顶部电极还具有通过化学机械抛光而平坦化的顶表面。在衬底上形成TiN的底部电极层，并且在随后的工艺步骤中形成通孔之前。第一电介质层形成在底电极层的上方，第二电介质层形成在第一电介质层上。通孔形成在延伸穿过第一和第二电介质层的选定部分。

83. 发明申请

US20070108430A1 Thermally contained/insulated phase change memory device and method (combined) 有权
标题翻译：含热/绝缘相变存储器件和方法（组合）
公开(公告)号：US20070108430A1
公开(公告)日：2007-05-17
申请号：US11338284
申请日：2006-01-24
申请人： Hsiang-Lan Lung
发明人： Hsiang-Lan Lung
IPC分类号： H01L47/00
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/1233 , H01L45/126 , H01L45/1293 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1675 , Y10S438/90
摘要： A memory device with improved heat transfer characteristics. The device first includes a dielectric material layer; first and second electrodes, vertically separated and having mutually opposed contact surfaces. A phase change memory element is encased within the dielectric material layer, including a phase-change layer positioned between and in electrical contact with the electrodes, wherein the lateral extent of the phase change layer is less than the lateral extent of the electrodes. An isolation material is positioned between the phase change layer and the dielectric layer, wherein the thermal conductivity of the isolation material is lower than the thermal conductivity of the dielectric material.
摘要翻译：具有改善的传热特性的记忆装置。该装置首先包括介电材料层; 第一和第二电极，垂直分离并具有相互相对的接触表面。相变存储元件被封装在电介质材料层内，包括位于电极之间并与之电接触的相变层，其中相变层的横向范围小于电极的横向范围。隔离材料位于相变层和电介质层之间，其中隔离材料的热导率低于介电材料的热导率。

84. 发明申请

US20070045708A1 Stacked bit line dual word line nonvolatile memory 有权
标题翻译：堆叠位线双字线非易失性存储器
公开(公告)号：US20070045708A1
公开(公告)日：2007-03-01
申请号：US11217659
申请日：2005-08-31
申请人： Hsiang-Lan Lung
发明人： Hsiang-Lan Lung
IPC分类号： H01L29/76
CPC分类号： H01L27/11206 , H01L21/76895 , H01L23/50 , H01L23/5252 , H01L27/0688 , H01L27/101 , H01L27/1021 , H01L27/1052 , H01L2924/0002 , H01L2924/00
摘要： An arrangement of nonvolatile memory devices, having at least one memory device level stacked level by level above a semiconductor substrate, each memory level comprising an oxide layer substantially disposed above a semiconductor substrate, a plurality of word lines substantially disposed above the oxide layer; a plurality of bit lines substantially disposed above the oxide layer; a plurality of via plugs substantially in electrical contact with the word lines and, an anti-fuse dielectric material substantially disposed on side walls beside the bit lines and substantially in contact with the plurality of bit lines side wall anti-fuse dielectrics.
摘要翻译：一种非易失性存储器件的布置，其具有至少一个在半导体衬底上层次级别堆叠的存储器件级，每个存储器级包括基本上设置在半导体衬底之上的氧化物层，基本上设置在氧化物层上方的多条字线; 基本上设置在所述氧化物层上方的多个位线; 基本上与字线电接触的多个通孔插塞和基本上设置在位线旁边的侧壁上且与多个位线侧壁反熔丝电介质基本上接触的抗熔丝电介质材料。

85. 发明授权

US07053406B1 One-time programmable read only memory and manufacturing method thereof 有权
标题翻译：一次性可编程只读存储器及其制造方法
公开(公告)号：US07053406B1
公开(公告)日：2006-05-30
申请号：US10907442
申请日：2005-04-01
申请人： ChiaHua Ho , Yen-Hao Shih , Hsiang-Lan Lung , Shih-Ping Hong , Shih-Chin Lee
发明人： ChiaHua Ho , Yen-Hao Shih , Hsiang-Lan Lung , Shih-Ping Hong , Shih-Chin Lee
IPC分类号： H01L29/72
CPC分类号： H01L27/1021 , H01L23/5252 , H01L27/12 , H01L2924/0002 , H01L2924/00
摘要： An one-time programmable read only memory is provided. An N-type doping region and a first P-type doping layer are disposed in a P-type semiconductor substrate sequentially. A second P-type doping layer is disposed between the first P-type doping layer and the N-type doping region. The second P-type doping layer with higher doping level, which has a linear structure, is served as a bit line. An electrically conductive layer is disposed over the P-type semiconductor substrate. The electrically conductive layer also has a linear structure that crosses over the first P-type doping layer. The first N-type doping layer is disposed in the P-type semiconductor substrate between the electrically conductive layer and the first P-type doping layer. The arrangement of N-type and P-type doping layer is used to be selective diode device. An anti-fuse layer is disposed between the electrically conductive layer and the first N-type doping layer.
摘要翻译：提供一次性可编程只读存储器。顺序地在P型半导体衬底中设置N型掺杂区和第一P型掺杂层。第二P型掺杂层设置在第一P型掺杂层和N型掺杂区之间。具有线性结构的具有较高掺杂度的第二P型掺杂层用作位线。导电层设置在P型半导体衬底上。导电层还具有与第一P型掺杂层交叉的线性结构。第一N型掺杂层设置在P型半导体衬底之间的导电层和第一P型掺杂层之间。 N型和P型掺杂层的布置用作选择性二极管器件。在导电层和第一N型掺杂层之间设置反熔丝层。

86. 发明授权

US06828081B2 Method and system for lithography using phase-change material 有权
公开(公告)号：US06828081B2
公开(公告)日：2004-12-07
申请号：US10315003
申请日：2002-12-10
申请人： Yi-Chou Chen , Chih-Yuan Lu , Hsiang-Lan Lung , Li-Hsin Chuang
发明人： Yi-Chou Chen , Chih-Yuan Lu , Hsiang-Lan Lung , Li-Hsin Chuang
IPC分类号： H01L2182
CPC分类号： H01L45/1213 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： Methods and systems are provided for forming an electrical interconnect layer between two layers of an integrated circuit. The interconnect layer is formed using a material having a first electrical conductivity corresponding to a first state and a second electrical conductivity corresponding to a second state, where the first electrical conductivity is different from the second electrical conductivity. An area of the material of the interconnect layer may be selected, for example, using a mask. Then energy may be applied to the selected area to change the electrical conductivity of the material in the selected area of the interconnect layer. Thus, the present invention may be used to implement optical memory devices which may be read by an electrical circuit.

87. 发明授权

US06750101B2 Method of manufacturing self-aligned, programmable phase change memory 有权
标题翻译：制造自对准可编程相变存储器的方法
公开(公告)号：US06750101B2
公开(公告)日：2004-06-15
申请号：US10278398
申请日：2002-10-23
申请人： Hsiang-Lan Lung
发明人： Hsiang-Lan Lung
IPC分类号： H01L21336
CPC分类号： G11C11/5678 , G11C11/56 , G11C13/0004 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1675
摘要： A self-aligned, nonvolatile memory structure based upon phase change materials, including chalcogenides, can be made with a very small area on an integrated circuit. The manufacturing process results in self-aligned memory cells requiring only two array-related masks defining the bit lines and word lines. Memory cells are defined at intersections of bit lines and word lines, and have dimensions that are defined by the widths of the bit lines and word lines in a self-aligned process. The memory cells comprise structures including a selection device, a heating/barrier plate layer and a phase change memory element, vertically arranged at the intersections of the bit lines and word lines.
摘要翻译：基于相变材料（包括硫族化物）的自对准非易失性存储器结构可以在集成电路上具有非常小的面积。制造过程导致自对准存储器单元仅需要限定位线和字线的两个阵列相关掩模。存储单元被定义在位线和字线的交点处，并且具有由自对准过程中位线和字线的宽度限定的尺寸。存储单元包括垂直布置在位线和字线的交点处的结构，包括选择装置，加热/屏障板层和相变存储元件。

88. 发明授权

US06285586B1 Nonvolatile static random access memory 有权
标题翻译：非易失性静态随机存取存储器
公开(公告)号：US06285586B1
公开(公告)日：2001-09-04
申请号：US09688767
申请日：2000-10-16
申请人： Hsiang-Lan Lung , Shue-Shuen Chen , Tung-Cheng Kuo
发明人： Hsiang-Lan Lung , Shue-Shuen Chen , Tung-Cheng Kuo
IPC分类号： G11C1604
CPC分类号： G11C14/00
摘要： A nonvolatile static random access memory adapted for a semiconductor substrate mainly comprises a nonvolatile erasable programmable memory transistor having a charge storage layer for storing data charges, and further having a first gate terminal, a first source terminal, and a first drain terminal, wherein the first gate terminal is connected to a word line, the first source terminal is connected to a power supply circuit through a first loader, and the first drain is connected to a first bit line; an access transistor having a second gate terminal, a second source terminal, and a second drain terminal, wherein the second gate terminal is connected to the word line, the second source terminal is connected to the power supply circuit through a second loader, and the second drain is connected to a second bit line; a first drive transistor having a third gate terminal, a third source terminal, and a third drain terminal, wherein the third gate terminal is connected to the second source terminal, the third source terminal is connected to ground, and the third drain terminal is connected to the first source terminal; a second drive transistor having a fourth gate terminal, a fourth source terminal, and a fourth drain terminal, wherein the fourth gate terminal is connected to the first source terminal, the fourth source terminal is connected to ground, and the fourth drain terminal is connected to the second source terminal; and a read control transistor having a fifth gate terminal, a fifth source terminal, and a fifth drain terminal, wherein the fifth gate terminal is connected to a control line, the fifth source terminal is connected to ground, and the fifth drain terminal is connected to the first bit line.
摘要翻译：适用于半导体衬底的非易失性静态随机存取存储器主要包括具有用于存储数据电荷的电荷存储层的不可擦除可编程存储晶体管，并且还具有第一栅极端子，第一源极端子和第一漏极端子，其中，第一栅极端子连接到字线，第一源极端子通过第一装载器连接到电源电路，并且第一漏极连接到第一位线; 具有第二栅极端子，第二源极端子和第二漏极端子的存取晶体管，其中所述第二栅极端子连接到所述字线，所述第二源极端子通过第二装载器连接到所述电源电路，第二漏极连接到第二位线; 具有第三栅极端子，第三源极端子和第三漏极端子的第一驱动晶体管，其中所述第三栅极端子连接到所述第二源极端子，所述第三源极端子接地，并且所述第三漏极端子连接到第一个源终端; 具有第四栅极端子，第四源极端子和第四漏极端子的第二驱动晶体管，其中所述第四栅极端子连接到所述第一源极端子，所述第四源极端子接地，并且所述第四漏极端子被连接到第二源终端; 以及具有第五栅极端子，第五源极端子和第五漏极端子的读取控制晶体管，其中所述第五栅极端子连接到控制线，所述第五源极端子接地，并且所述第五漏极端子被连接到第一位。

89. 发明授权

US09082954B2 PCRAM with current flowing laterally relative to axis defined by electrodes 有权
标题翻译： PCRAM，其电流相对于由电极限定的轴线横向流动
公开(公告)号：US09082954B2
公开(公告)日：2015-07-14
申请号：US13210020
申请日：2011-08-15
申请人： Hsiang-Lan Lung , Chung Hon Lam
发明人： Hsiang-Lan Lung , Chung Hon Lam
IPC分类号： G11C11/00 , H01L45/00
CPC分类号： H01L45/06 , H01L45/1246 , H01L45/144 , H01L45/16
摘要： An improved phase change memory device has a phase change structure including a thin part between a contact surface of an electrode and a dielectric structure. For example, the thin part has a maximum thickness that is smaller than a maximum width of the contact surface of the electrode. In another example, the phase change structure surrounds the dielectric structure. Several variations improve the contact between the phase change structure and an electrode.
摘要翻译：改进的相变存储器件具有包括电极的接触表面和电介质结构之间的薄部分的相变结构。例如，薄部具有比电极的接触表面的最大宽度小的最大厚度。在另一示例中，相变结构围绕电介质结构。几种变化改善了相变结构和电极之间的接触。

90. 发明授权

US08946671B2 Mask read only memory containing diodes and method of manufacturing the same 有权
标题翻译：掩模只读存储器二极管及其制造方法
公开(公告)号：US08946671B2
公开(公告)日：2015-02-03
申请号：US10642244
申请日：2003-08-18
申请人： Sheng-Chih Lai , Hsiang-Lan Lung , Yi-Chou Chen
发明人： Sheng-Chih Lai , Hsiang-Lan Lung , Yi-Chou Chen
IPC分类号： H01L47/00 , H01L27/102 , H01L21/822 , H01L27/06
CPC分类号： H01L27/1021 , H01L21/8221 , H01L27/0688
摘要： A mask read only memory containing diodes and method of manufacturing the same. The mask read only memory is a high-density three dimensional array formed by stacking a plurality of diode layers and the logic “0” or “1” is defined by whether there is a dielectric layer on the diode.
摘要翻译：掩模只读存储器二极管及其制造方法。掩模只读存储器是通过堆叠多个二极管层形成的高密度三维阵列，并且逻辑“0”或“1”由二极管上是否存在介电层来定义。

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