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81. 发明授权

US07546416B2 Method for substantially uninterrupted cache readout 有权
标题翻译：基本上不间断高速缓存读取的方法
公开(公告)号：US07546416B2
公开(公告)日：2009-06-09
申请号：US11474436
申请日：2006-06-26
申请人： Aaron Yip
发明人： Aaron Yip
IPC分类号： G06F13/00 , G11C7/00
CPC分类号： G06F12/0811
摘要： A memory device capable of sequentially outputting multiple pages of cached data while mitigating any interruption typically caused by fetching and transferring operations. The memory device outputs cached data from a first page while data from a second page is fetched into sense amplifier circuitry. When the outputting of the first page reaches a predetermined transfer point, a portion of the fetched data from the second page is transferred into the cache at the same time the remainder of the cached first page is being output. The remainder of the second page is transferred into the cache after all of the data from the first page is output while the outputting of the first portion of the second page begins with little or no interruption.
摘要翻译：一种能够顺利地输出多页缓存数据同时减轻通常由取样和传送操作引起的任何中断的存储器件。存储器件从第一页输出缓存的数据，而来自第二页的数据被提取到读出放大器电路中。当第一页的输出到达预定的传送点时，来自第二页的获取的数据的一部分在被缓存的第一页的其余部分被输出的同时被传送到高速缓存。在第二页的第一部分的输出以很少或没有中断的情况下开始输出来自第一页的所有数据之后，第二页的其余部分被传送到高速缓存。

82. 发明申请

US20080151638A1 SELECTIVE THRESHOLD VOLTAGE VERIFICATION AND COMPACTION 有权
标题翻译：选择性阈值电压验证和压缩
公开(公告)号：US20080151638A1
公开(公告)日：2008-06-26
申请号：US12042021
申请日：2008-03-04
申请人： Aaron Yip
发明人： Aaron Yip
IPC分类号： G11C16/34 , G11C16/10
CPC分类号： G11C16/0483 , G11C16/3404 , G11C16/344 , G11C16/3445
摘要： Non-volatile memory devices for providing selective compaction verification and/or selective compaction to facilitate a tightening of the distribution of threshold voltages in memory devices utilizing a NAND architecture. By providing for compaction verification and/or compaction on less than all word lines of a NAND string, increased tightening of the distribution may be achieved over prior methods performed concurrently on all word lines of a NAND string.
摘要翻译：用于提供选择性压实验证和/或选择性压缩的非易失性存储器件，以利于利用NAND架构在存储器件中紧固阈值电压分布。通过在NAND串的不到所有字线上提供压缩验证和/或压缩，可以通过在NAND串的所有字线上同时执行的现有方法来实现分配的增加的紧缩。

83. 发明申请

US20070183202A1 Memory array segmentation and methods 有权
标题翻译：内存阵列分割和方法
公开(公告)号：US20070183202A1
公开(公告)日：2007-08-09
申请号：US11349854
申请日：2006-02-08
申请人： Aaron Yip
发明人： Aaron Yip
IPC分类号： G11C14/00 , G11C16/04 , G11C5/06 , G11C11/34
CPC分类号： G11C16/0483 , H01L27/115
摘要： The invention provides methods and apparatus. A memory array has a first well region having a first conductivity type. A plurality of second well regions of a second conductivity type is formed in the first well region. The second well regions are electrically isolated from each other. A plurality of memory cells, arranged in row and column fashion, is formed on each second well region. Corresponding rows of memory cells of the respective second well regions are commonly coupled to a word line.
摘要翻译：本发明提供了方法和装置。存储器阵列具有第一导电类型的第一阱区。在第一阱区中形成有第二导电类型的多个第二阱区。第二阱区彼此电隔离。在每个第二阱区域上形成以行和列方式布置的多个存储单元。相应的第二阱区的存储单元的相应行通常耦合到字线。

84. 发明申请

US20060023504A1 Non-volatile programmable fuse apparatus in a memory device 有权
标题翻译：非易失性可编程保险丝装置在存储装置中
公开(公告)号：US20060023504A1
公开(公告)日：2006-02-02
申请号：US11067974
申请日：2005-02-28
申请人： Aaron Yip
发明人： Aaron Yip
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/0441
摘要： The non-volatile, programmable fuse apparatus has a pair of p-channel transistors coupled in a latch configuration. A supercell is coupled between each transistor and ground. Each supercell is comprised of a plurality of non-volatile memory cells that are each programmed substantially similarly for each supercell. The supercells are programmed in a complementary fashion. The output state of the apparatus is determined by the state of the supercell to which the output is coupled.
摘要翻译：非易失性可编程保险丝装置具有以闩锁配置耦合的一对p沟道晶体管。超级单元耦合在每个晶体管和地之间。每个超级单元由多个非易失性存储器单元组成，每个非易失性存储单元的每个超级单元的编程基本相似。超级单元以互补的方式进行编程。设备的输出状态由输出耦合到的超级单元的状态决定。

85. 发明授权

US09135998B2 Sense operation flags in a memory device 有权
标题翻译：存储设备中的检测操作标志
公开(公告)号：US09135998B2
公开(公告)日：2015-09-15
申请号：US12942152
申请日：2010-11-09
申请人： Shafqat Ahmed , Khaled Hasnat , Pranav Kalavade , Krishna Parat , Aaron Yip , Mark A. Helm , Andrew Bicksler
发明人： Shafqat Ahmed , Khaled Hasnat , Pranav Kalavade , Krishna Parat , Aaron Yip , Mark A. Helm , Andrew Bicksler
IPC分类号： G06F12/00 , G11C16/04 , G11C16/24 , G11C16/26
CPC分类号： G06F3/0625 , G06F3/061 , G06F3/0653 , G06F3/0665 , G06F3/0688 , G06F3/0689 , G06F12/0804 , G06F12/0846 , G06F13/28 , G06F2212/2022 , G06F2212/224 , G06F2212/461 , G11C16/0483 , G11C16/24 , G11C16/26 , Y02D10/14
摘要： Memory devices, methods for programming sense flags, methods for sensing flags, and memory systems are disclosed. In one such memory device, the odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. The even bit lines of the flag memory cell array are disconnected from the dynamic data cache. When an even page of a main memory cell array is read, the odd flag memory cells, comprising flag data, are read at the same time so that it can be determined whether the odd page of the main memory cell array has been programmed. If the flag data indicates that the odd page has not been programmed, threshold voltage windows can be adjusted to determine the states of the sensed even memory cell page.
摘要翻译：公开了存储器件，用于编程感测标志的方法，用于感测标志的方法和存储器系统。在一个这样的存储器件中，标志存储器单元阵列的奇数位线与短路连接到动态数据高速缓存。标记存储单元阵列的偶数位线与动态数据高速缓存断开连接。当读取主存储单元阵列的偶数页时，同时读取包括标志数据的奇数标志存储单元，以便可以确定主存储单元阵列的奇数页是否已被编程。如果标志数据指示奇数页未被编程，则可以调整阈值电压窗口以确定感测到的偶数存储单元页的状态。

86. 发明授权

US08542534B2 Select gate programming in a memory device 有权
标题翻译：在存储设备中选择门编程
公开(公告)号：US08542534B2
公开(公告)日：2013-09-24
申请号：US12756366
申请日：2010-04-08
申请人： Shigekazu Yamada , Aaron Yip
发明人： Shigekazu Yamada , Aaron Yip
IPC分类号： G11C11/34
CPC分类号： G11C16/102 , G11C16/0483 , G11C16/24 , G11C16/3427
摘要： Methods for programming select gates, memory devices, and memory systems are disclosed. In one such method for programming, a program inhibit voltage is transferred from a source line to unselected bit lines. Bit line-to-bit line capacitance, between the unselected bit lines and selected bit lines to be program inhibited, boosts the bit line voltage of the selected, inhibited bit lines to a target inhibit voltage. In one embodiment, the voltage on the selected, inhibited bit line can be increased in a plurality of inhibit steps whereby either one, two, or all of the steps can be used during the programming of unprogrammed select gates.
摘要翻译：公开了用于编程选择门，存储器件和存储器系统的方法。在一种用于编程的方法中，程序禁止电压从源极线传送到未选位线。在未被选择的位线和要被编程禁止的选定位线之间的位线对位线电容将所选择的禁止位线的位线电压升高到目标抑制电压。在一个实施例中，可以在多个禁止步骤中增加所选择的禁止位线上的电压，由此在编程的未选择栅极的编程期间可以使用一个，两个或所有步骤。

87. 发明授权

US08125836B2 Verifying an erase threshold in a memory device 有权
标题翻译：验证存储器设备中的擦除阈值
公开(公告)号：US08125836B2
公开(公告)日：2012-02-28
申请号：US13153746
申请日：2011-06-06
申请人： Aaron Yip
发明人： Aaron Yip
IPC分类号： G11C16/04
CPC分类号： G11C16/344
摘要： In one or more embodiments, a memory device is disclosed as having an erase verify operation that includes a negative bias on the p-well in which the memory cell or cells being erased are formed. After an erase pulse is applied to the selected cells to be erased, the p-well is biased with the negative voltage and the erase verify operation is performed to determine the erased state of the cell(s).
摘要翻译：在一个或多个实施例中，公开了一种存储器件，其具有擦除验证操作，该擦除验证操作包括在其上形成有擦除存储器单元的p阱上的负偏压。在将擦除脉冲施加到要擦除的所选择的单元之后，p阱被以负电压偏置，并执行擦除验证操作以确定单元的擦除状态。

88. 发明授权

US08111549B2 Dynamic wordline start voltage for nand programming 有权
标题翻译： nand编程的动态字线启动电压
公开(公告)号：US08111549B2
公开(公告)日：2012-02-07
申请号：US12460073
申请日：2009-07-13
申请人： Aaron Yip
发明人： Aaron Yip
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/3418
摘要： The present invention discloses a method of programming an MLC NAND flash memory device comprising: selecting a start value for a program voltage for a lower page; incrementing said program voltage to program said lower page; verifying a threshold voltage; determining said program voltage to achieve a desired value for said threshold voltage; applying an offset to said program voltage; and obtaining a start value for said program voltage for an upper page.
摘要翻译：本发明公开了一种编程MLC NAND闪速存储器件的方法，包括：为下页选择编程电压的起始值; 递增所述程序电压以对所述下页进行编程; 验证阈值电压; 确定所述编程电压以达到所述阈值电压的期望值; 对所述编程电压施加偏移; 并获得用于上一页的所述编程电压的起始值。

89. 发明授权

US07957198B2 Verifying an erase threshold in a memory device 有权
标题翻译：验证存储器设备中的擦除阈值
公开(公告)号：US07957198B2
公开(公告)日：2011-06-07
申请号：US12762640
申请日：2010-04-19
申请人： Aaron Yip
发明人： Aaron Yip
IPC分类号： G11C16/06
CPC分类号： G11C16/344
摘要： In one or more embodiments, a memory device is disclosed as having an erase verify operation that includes a negative bias on the p-well in which the memory cell or cells being erased are formed. After an erase pulse is applied to the selected cells to be erased, the p-well is biased with the negative voltage and the erase verify operation is performed to determine the erased state of the cell(s).
摘要翻译：在一个或多个实施例中，公开了一种存储器件，其具有擦除验证操作，该擦除验证操作包括在其上形成有擦除存储器单元的p阱上的负偏压。在将擦除脉冲施加到要擦除的所选择的单元之后，p阱被以负电压偏置，并执行擦除验证操作以确定单元的擦除状态。

90. 发明申请

US20100061155A1 MEMORY ARRAY SEGMENTATION AND METHODS 有权
标题翻译：记忆阵列分段和方法
公开(公告)号：US20100061155A1
公开(公告)日：2010-03-11
申请号：US12614750
申请日：2009-11-09
申请人： Aaron Yip
发明人： Aaron Yip
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , H01L27/115
摘要： An embodiment of a method includes applying a first voltage to a selected word line commonly coupled to portions of a row of memory cells respectively formed on first well regions of a plurality of first well regions of a first conductivity type formed in a second well region of a second conductivity type, at least one target memory cell coupled to the selected word line and formed on one of the first well regions, the first well regions electrically isolated from each other; applying a second voltage to unselected word lines, each unselected word line commonly coupled to portions of a row of memory cells not targeted for programming and respectively formed on the first well regions; and applying a third voltage to those first well regions that do not include the at least one target memory cell.
摘要翻译：一种方法的实施例包括将第一电压施加到通常耦合到分别形成在第一导电类型的多个第一阱区域的第一阱区域上的存储器单元行的部分的选定字线，所述第一阱区域形成在第一阱区域的第二阱区域中，第二导电类型，耦合到所选字线并形成在第一阱区之一上的至少一个目标存储单元，第一阱区彼此电隔离; 对未选择的字线施加第二电压，每个未选择的字线共同耦合到一行存储器单元的未被编程并分别形成在第一阱区上的部分; 以及向不包括所述至少一个目标存储单元的所述第一阱区施加第三电压。

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