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81. 发明申请

US20120313242A1 SUBSTRATE AND ASSEMBLY THEREOF WITH DIELECTRIC REMOVAL FOR INCREASED POST HEIGHT 有权
标题翻译：基板和组件，用于提高后置高度的电介质去除
公开(公告)号：US20120313242A1
公开(公告)日：2012-12-13
申请号：US13155845
申请日：2011-06-08
申请人： Kazuo Sakuma , Philip Damberg , Belgacem Haba
发明人： Kazuo Sakuma , Philip Damberg , Belgacem Haba
IPC分类号： H01L23/48 , H01L21/60 , H01L21/768
CPC分类号： H01L21/4853 , H01L23/3142 , H01L23/498 , H01L23/49816 , H01L23/49838 , H01L24/01 , H01L24/15 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/16225 , H01L2224/16238 , H01L2224/32225 , H01L2224/73204 , H01L2224/81192 , H01L2224/81193 , H01L2224/81801 , H01L2924/01013 , H01L2924/01028 , H01L2924/01029 , H01L2924/01079 , H01L2924/014 , H01L2924/09701 , H01L2924/12042 , H01L2924/2064 , H01L2924/20641 , H05K1/0284 , H05K1/0306 , H05K1/09 , H05K3/002 , H05K2201/0166 , H01L2924/00
摘要： An interconnection substrate includes a plurality of electrically conductive elements of at least one wiring layer defining first and second lateral directions. Electrically conductive projections for bonding to electrically conductive contacts of at least one component external to the substrate, extend from the conductive elements above the at least one wiring layer. The conductive projections have end portions remote from the conductive elements and neck portions between the conductive elements and the end portions. The end portions have lower surfaces extending outwardly from the neck portions in at least one of the lateral directions. The substrate further includes a dielectric layer overlying the conductive elements and extending upwardly along the neck portions at least to the lower surfaces. At least portions of the dielectric layer between the conductive projections are recessed below a height of the lower surfaces.
摘要翻译：互连衬底包括限定第一和第二横向方向的至少一个布线层的多个导电元件。导电突起，用于粘合到基板外部的至少一个部件的导电触点，从导电元件延伸到至少一个布线层之上。导电突起具有远离导电元件的端部和导电元件与端部之间的颈部。端部具有在至少一个横向方向上从颈部部分向外延伸的下表面。衬底还包括覆盖导电元件并且沿着颈部部分至少向下表面向上延伸的电介质层。导电突起之间的电介质层的至少部分凹陷在下表面的高度之下。

82. 发明申请

US20120313238A1 SEMICONDUCTOR CHIP PACKAGE ASSEMBLY AND METHOD FOR MAKING SAME 有权
标题翻译：半导体芯片封装组件及其制造方法
公开(公告)号：US20120313238A1
公开(公告)日：2012-12-13
申请号：US13155552
申请日：2011-06-08
申请人： Hiroaki Sato , Yukio Hashimoto , Yoshikuni Nakadaira , Norihito Masuda , Belgacem Haba , Ilyas Mohammed , Philip Damberg
发明人： Hiroaki Sato , Yukio Hashimoto , Yoshikuni Nakadaira , Norihito Masuda , Belgacem Haba , Ilyas Mohammed , Philip Damberg
IPC分类号： H01L23/498 , H01L21/56
CPC分类号： H01L21/561 , H01L21/4857 , H01L21/568 , H01L23/3128 , H01L23/49811 , H01L23/49822 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00
摘要： A microelectronic assembly may include a substrate containing a dielectric element having first and second opposed surfaces. The dielectric element may include a first dielectric layer adjacent the first surface, and a second dielectric layer disposed between the first dielectric layer and the second surface. A Young's modulus of the first dielectric layer may be at least 50% greater than the Young's modulus of the second dielectric layer, which is less than two gigapascal (GPa). A conductive structure may extend through the first and second dielectric layers and electrically connect substrate contacts at the first surface with terminals at the second surface. The substrate contacts may be joined with contacts of a microelectronic element through conductive masses, and a rigid underfill may be between the microelectronic element and the first surface. The terminals may be usable to bond the microelectronic assembly to contacts of a component external to the microelectronic assembly.
摘要翻译：微电子组件可以包括含有具有第一和第二相对表面的电介质元件的衬底。电介质元件可以包括与第一表面相邻的第一电介质层，以及设置在第一介电层和第二表面之间的第二电介质层。第一电介质层的杨氏模量可以比第二电介质层的杨氏模量大至少50％，小于二千兆帕（GPa）。导电结构可以延伸穿过第一和第二电介质层，并且将第一表面处的基板触点与第二表面上的端子电连接。衬底触点可以通过导电块与微电子元件的触点接合，并且刚性底部填充可以在微电子元件和第一表面之间。端子可以用于将微电子组件接合到微电子组件外部的部件的触点。

83. 发明申请

US20120273933A1 THREE-DIMENSIONAL SYSTEM-IN-A-PACKAGE 有权
标题翻译：三维系统包装
公开(公告)号：US20120273933A1
公开(公告)日：2012-11-01
申请号：US13097943
申请日：2011-04-29
申请人： Vage Oganesian , Belgacem Haba , Ilyas Mohammed , Piyush Savalia , Craig Mitchell
发明人： Vage Oganesian , Belgacem Haba , Ilyas Mohammed , Piyush Savalia , Craig Mitchell
IPC分类号： H01L23/12 , H01L21/58 , H01L23/488
CPC分类号： H01L25/50 , H01L23/5389 , H01L24/24 , H01L24/82 , H01L24/97 , H01L25/0657 , H01L2224/24145 , H01L2224/32145 , H01L2224/32225 , H01L2224/73267 , H01L2225/06524 , H01L2924/01005 , H01L2924/01006 , H01L2924/01023 , H01L2924/01033 , H01L2924/01087 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/1434 , H01L2924/1436 , H01L2924/1437 , H01L2924/00
摘要： A microelectronic assembly can include first, second and third stacked substantially planar elements, e.g., of dielectric or semiconductor material, and which may have a CTE of less than 10 ppm/° C. The assembly may be a microelectronic package and may incorporate active semiconductor devices in one, two or more of the first, second or third elements to function cooperatively as a system-in-a-package. In one example, an electrically conductive element having a minimum thickness less than 10 microns, may be formed by plating, and may electrically connect two or more of the first, second or third elements. The conductive element may entirely underlie a surface of another one of the substantially planar elements.
摘要翻译：微电子组件可以包括例如电介质或半导体材料的第一，第二和第三堆叠的基本平坦的元件，并且其可以具有小于10ppm /℃的CTE。组件可以是微电子封装，并且可以并入有源半导体在第一，第二或第三元件中的一个，两个或更多个元件中的装置可以协同地作为系统级封装。在一个示例中，具有最小厚度小于10微米的导电元件可以通过电镀形成，并且可以电连接第一，第二或第三元件中的两个或更多个。导电元件可以完全位于另一个基本上平面的元件的表面之下。

84. 发明申请

US20120267751A1 INTERPOSER HAVING MOLDED LOW CTE DIELECTRIC 有权
标题翻译：具有成型低CTE电介质的插件
公开(公告)号：US20120267751A1
公开(公告)日：2012-10-25
申请号：US13091800
申请日：2011-04-21
申请人： Belgacem Haba , Ilyas Mohammed
发明人： Belgacem Haba , Ilyas Mohammed
IPC分类号： H01L23/482 , H01L27/02 , H01L21/28
CPC分类号： H01L21/486 , H01L23/49827 , H01L23/49861 , H01L23/49894 , H01L2224/16225 , H01L2924/09701 , H01L2924/15311 , H05K3/4046 , H05K2201/0979 , H05K2201/10378 , H05K2201/10674
摘要： A method for making an interconnection component is disclosed, including forming a plurality of metal posts extending away from a reference surface. Each post is formed having a pair of opposed end surface and an edge surface extending therebetween. A dielectric layer is formed contacting the edge surfaces and filling spaces between adjacent ones of the posts. The dielectric layer has first and second opposed surfaces adjacent the first and second end surfaces. The dielectric layer has a coefficient of thermal expansion of less than 8 ppm/° C. The interconnection component is completed such that it has no interconnects between the first and second end surfaces of the posts that extend in a lateral direction. First and second pluralities of wettable contacts are adjacent the first and second opposed surfaces. The wettable contacts are usable to bond the interconnection component to a microelectronic element or a circuit panel.
摘要翻译：公开了一种用于制造互连部件的方法，包括形成远离参考表面延伸的多个金属柱。每个柱形成具有一对相对的端面和在它们之间延伸的边缘表面。形成接触边缘表面和相邻柱之间的填充空间的电介质层。电介质层具有邻近第一和第二端面的第一和第二相对表面。电介质层的热膨胀系数小于8ppm /℃。互连部件完成，使得它们在横向方向上延伸的柱的第一和第二端面之间没有互连。第一和第二多个可湿接触部分邻近第一和第二相对表面。可湿接触可用于将互连部件连接到微电子元件或电路板。

85. 发明授权

US08278764B1 Stub minimization for multi-die wirebond assemblies with orthogonal windows 有权
标题翻译：具有正交窗口的多芯片接线组件的短截线最小化
公开(公告)号：US08278764B1
公开(公告)日：2012-10-02
申请号：US13354772
申请日：2012-01-20
申请人： Richard Dewitt Crisp , Wael Zohni , Belgacem Haba , Frank Lambrecht
发明人： Richard Dewitt Crisp , Wael Zohni , Belgacem Haba , Frank Lambrecht
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L25/105 , H01L23/13 , H01L23/3128 , H01L25/0652 , H01L25/0655 , H01L2224/0401 , H01L2224/04042 , H01L2224/06136 , H01L2224/16225 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/4824 , H01L2224/73215 , H01L2225/0651 , H01L2225/06562 , H01L2225/1023 , H01L2225/107 , H01L2924/01087 , H01L2924/01322 , H01L2924/09701 , H01L2924/15311 , H01L2924/157 , H01L2924/15787 , H01L2924/15788 , H01L2924/1579 , H01L2924/19041 , H01L2924/19105 , H01L2924/19106 , H01L2924/3011 , H01L2924/00012 , H01L2924/00
摘要： A microelectronic package can include a substrate having first, second, and third apertures extending between first and second surfaces thereof, first, second, and third microelectronic elements each having a surface facing the first surface, and a plurality of terminals exposed at a central region of the second surface. The apertures can have first, second, and third axes extending in directions of the lengths of the respective apertures. The first and second axes can be parallel to one another. The third axis can be transverse to the first axis. The central region of the second surface of the substrate can be disposed between the first and second axes. The terminals can be configured to carry sufficient address information usable by circuitry within the package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within at least one of the microelectronic elements.
摘要翻译：微电子封装可以包括具有在其第一和第二表面之间延伸的第一，第二和第三孔的衬底，每个具有面向第一表面的表面的第一，第二和第三微电子元件，以及暴露在中心区域处的多个端子的第二个表面。孔可以具有在相应孔的长度方向上延伸的第一，第二和第三轴。第一和第二轴线可以彼此平行。第三轴线可以横向于第一轴线。基板的第二表面的中心区域可以设置在第一和第二轴线之间。终端可被配置为承载可用于封装内的电路的足够的地址信息，以从至少一个微电子元件内的存储器存储阵列的所有可寻址的存储单元中确定可寻址的存储器位置。

86. 发明授权

US08241959B2 Microelectronic packages fabricated at the wafer level and methods therefor 有权
标题翻译：在晶圆级制造的微电子封装及其方法
公开(公告)号：US08241959B2
公开(公告)日：2012-08-14
申请号：US12829709
申请日：2010-07-02
申请人： Belgacem Haba , Giles Humpston
发明人： Belgacem Haba , Giles Humpston
IPC分类号： H01L21/00
CPC分类号： H01L23/525 , H01L23/3114 , H01L24/11 , H01L24/13 , H01L24/48 , H01L2224/0401 , H01L2224/05599 , H01L2224/0603 , H01L2224/11 , H01L2224/114 , H01L2224/1147 , H01L2224/116 , H01L2224/13 , H01L2224/13099 , H01L2224/1403 , H01L2224/32225 , H01L2224/48091 , H01L2224/4824 , H01L2224/484 , H01L2224/73215 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/014 , H01L2924/10253 , H01L2924/15311 , H01L2924/15312 , H01L2924/15787 , H01L2924/30105 , H01L2924/30107 , H01L2924/00 , H01L2224/45099 , H01L2224/85399
摘要： A method of making microelectronic packages includes making a subassembly by providing a plate having a top surface, a bottom surface and openings extending between the top and bottom surfaces, attaching a compliant layer to the top surface of the plate, the compliant layer having openings that are aligned with the openings extending through the plate, and providing electrically conductive features on the compliant layer. After making the subassembly, the bottom surface of the plate is attached with the top surface of a semiconductor wafer so that the openings extending through the plate are aligned with contacts on the wafer. At least some of the electrically conductive features on the compliant layer are electrically interconnected with the contacts on the semiconductor wafer.
摘要翻译：制造微电子封装的方法包括通过提供具有顶表面，底表面和在顶表面和底表面之间延伸的开口的板来制造子组件，将柔性层附接到板的顶表面，顺应层具有开口，与延伸穿过板的开口对齐，并且在柔性层上提供导电特征。在制造子组件之后，板的底表面与半导体晶片的顶表面相连，使得延伸穿过该板的开口与晶片上的触点对准。柔性层上的至少一些导电特征与半导体晶片上的触点电互连。

87. 发明申请

US20120152433A1 DUAL WAFER SPIN COATING 有权
标题翻译：双面旋涂
公开(公告)号：US20120152433A1
公开(公告)日：2012-06-21
申请号：US12974611
申请日：2010-12-21
申请人： Vage Oganesian , Belgacem Haba , Ilyas Mohammed , Piyush Savalia , Craig Mitchell
发明人： Vage Oganesian , Belgacem Haba , Ilyas Mohammed , Piyush Savalia , Craig Mitchell
IPC分类号： B32B37/06
CPC分类号： H01L22/12 , H01L21/67092
摘要： A method of bonding a first substrate and a second substrate includes the steps of rotating first substrate with an adhesive mass thereon, and second substrate contacting the mass and overlying the first substrate, controlling a vertical height of a heated control platen spaced apart from and not contacting the second substrate so as to control a temperature of the adhesive mass, so as to at least one of bond the first and second substrates in alignment with one another, or achieve a sufficiently planar adhesive interface between the first and second substrates.
摘要翻译：接合第一基板和第二基板的方法包括以下步骤：使第一基板与其上的粘合剂质量物质旋转，第二基板接触物料并覆盖第一基板，控制加热的控制台板的垂直高度，使所述第二基板接触以控制所述粘合剂物料的温度，以便使所述第一和第二基板彼此对准的至少一个接合，或在所述第一和第二基板之间实现足够平坦的粘合界面。

88. 发明申请

US20120146206A1 PIN ATTACHMENT 审中-公开
标题翻译： PIN码附件
公开(公告)号：US20120146206A1
公开(公告)日：2012-06-14
申请号：US12966225
申请日：2010-12-13
申请人： Belgacem Haba , Ilyas Mohammed
发明人： Belgacem Haba , Ilyas Mohammed
IPC分类号： H01L23/52 , H01L21/50 , H01L23/532
CPC分类号： H01L24/81 , H01L21/4853 , H01L21/486 , H01L21/563 , H01L23/3121 , H01L23/49811 , H01L23/5389 , H01L24/48 , H01L24/73 , H01L24/97 , H01L25/105 , H01L25/50 , H01L2224/11003 , H01L2224/16225 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2224/811 , H01L2224/81801 , H01L2224/97 , H01L2225/1023 , H01L2225/1058 , H01L2225/1088 , H01L2924/00014 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A microelectronic package includes a substrate having a first region, a second region, a first surface, and a second surface remote from the first surface. At least one microelectronic element overlies the first region on the first surface. First electrically conductive elements are exposed at one of the first surface and the second surface of the substrate within the second region with at least some of the first conductive elements electrically connected to the at least one microelectronic element. Substantially rigid metal elements overlie the first conductive elements and have end surfaces remote therefrom. A bond metal joins the metal elements with the first conductive elements, and a molded dielectric layer overlies at least the second region of the substrate and has a surface remote from the substrate. The end surfaces of the metal elements are at least partially exposed at the surface of the molded dielectric layer.
摘要翻译：微电子封装包括具有第一区域，第二区域，第一表面和远离第一表面的第二表面的衬底。至少一个微电子元件覆盖在第一表面上的第一区域上。第一导电元件在第二区域内的衬底的第一表面和第二表面中的一个处暴露，其中至少一些第一导电元件电连接到至少一个微电子元件。基本上刚性的金属元件覆盖在第一导电元件上并具有远离其的端表面。键合金属将金属元件与第一导电元件结合，并且模制的电介质层至少覆盖在衬底的第二区域上并且具有远离衬底的表面。金属元件的端面至少部分地暴露在模制介电层的表面。

89. 发明授权

US08193615B2 Semiconductor packaging process using through silicon vias 有权
标题翻译：半导体封装工艺使用硅通孔
公开(公告)号：US08193615B2
公开(公告)日：2012-06-05
申请号：US12221204
申请日：2008-07-31
申请人： Belgacem Haba , Giles Humpston , Moti Margalit
发明人： Belgacem Haba , Giles Humpston , Moti Margalit
IPC分类号： H01L23/485
CPC分类号： H01L21/76898 , H01L21/76805 , H01L23/3114 , H01L23/481 , H01L24/12 , H01L24/24 , H01L24/82 , H01L24/95 , H01L24/96 , H01L25/0657 , H01L25/50 , H01L2224/02372 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/13024 , H01L2224/13025 , H01L2224/2518 , H01L2224/82039 , H01L2225/06513 , H01L2225/06541 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/10329 , H01L2924/12042 , H01L2924/12044 , H01L2924/00
摘要： A microelectronic unit 400 can include a semiconductor element 401 having a front surface, a microelectronic semiconductor device adjacent to the front surface, contacts 403 at the front surface and a rear surface remote from the front surface. The semiconductor element 401 can have through holes 410 extending from the rear surface through the semiconductor element 401 and through the contacts 403. A dielectric layer 411 can line the through holes 410. A conductive layer 412 may overlie the dielectric layer 411 within the through holes 410. The conductive layer 412 can conductively interconnect the contacts 403 with unit contacts.
摘要翻译：微电子单元400可以包括具有前表面的半导体元件401，与前表面相邻的微电子半导体器件，在前表面处的触点403和远离前表面的后表面。半导体元件401可以具有从后表面延伸通过半导体元件401并通过触点403的通孔410.电介质层411可以使通孔410线化。导电层412可覆盖通孔内的电介质层411 导电层412可以将触点403与单元触点导电地互连。

90. 发明申请

US20120119367A1 CONDUCTIVE PADS DEFINED BY EMBEDDED TRACES 有权
公开(公告)号：US20120119367A1
公开(公告)日：2012-05-17
申请号：US12963938
申请日：2010-12-09
申请人： Belgacem Haba
发明人： Belgacem Haba
IPC分类号： H01L23/498 , H01L21/60
CPC分类号： H01L24/05 , H01L23/49838 , H01L24/03 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L25/0657 , H01L2224/03001 , H01L2224/03003 , H01L2224/0311 , H01L2224/0401 , H01L2224/04026 , H01L2224/05551 , H01L2224/05552 , H01L2224/05555 , H01L2224/05568 , H01L2224/0557 , H01L2224/05571 , H01L2224/05572 , H01L2224/05576 , H01L2224/05644 , H01L2224/05655 , H01L2224/05686 , H01L2224/0569 , H01L2224/13022 , H01L2224/13023 , H01L2224/16145 , H01L2224/16221 , H01L2224/29018 , H01L2224/29026 , H01L2224/32145 , H01L2224/32225 , H01L2225/06513 , H01L2225/06541 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/1032 , H01L2924/10329 , H01L2924/1037 , H01L2924/1203 , H01L2924/12042 , H01L2924/1304 , H01L2924/14 , H01L2924/1433 , H01L2924/1436 , H01L2924/1437 , H01L2924/1461 , H01L2924/20107 , H01L2924/00014 , H01L2924/00
摘要： An assembly and method of making same are provided. The assembly can include a first component including a dielectric region having an exposed surface, a conductive pad at the surface defined by a conductive element having at least a portion extending in an oscillating or spiral path along the surface, and a an electrically conductive bonding material joined to the conductive pad and bridging an exposed portion of the dielectric surface between adjacent segments. The conductive pad can permit electrical interconnection of the first component with a second component having a terminal joined to the pad through the electrically conductive bonding material. The path of the conductive element may or may not overlap or cross itself.

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