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81. 发明授权

US07697600B2 Programmable receiver equalization circuitry and methods 有权
标题翻译：可编程接收机均衡电路和方法
公开(公告)号：US07697600B2
公开(公告)日：2010-04-13
申请号：US11182658
申请日：2005-07-14
申请人： Simardeep Maangat , Sergey Shumarayev , Wilson Wong , ThuNgoc Tran
发明人： Simardeep Maangat , Sergey Shumarayev , Wilson Wong , ThuNgoc Tran
IPC分类号： H03H7/30
CPC分类号： H04L25/03885 , H04B3/04 , H04L25/03019
摘要： Data signals transmitted over transmission media suffer from attenuation caused by the transmission media. Equalization circuitry may be provided to compensate for attenuation caused by the transmission media. Equalization circuitry may include multiple stages arranged in series to allow the frequency responses of the stages to aggregate together. Each stage may be programmable to insert a zero, which causes the frequency response of the stage to increase in magnitude by 20 dB/decade. The frequency location of the zero may also be programmable to allow each stage to contribute a certain amount of gain for a specific frequency. Each stage may also be programmable to determine the location of poles for reduction of high frequency noise and cross-talk cancellation.
摘要翻译：通过传输介质传输的数据信号遭受由传输介质引起的衰减。可以提供均衡电路以补偿由传输介质引起的衰减。均衡电路可以包括串联布置的多个级，以允许级的频率响应聚合在一起。每个级可以是可编程的，以插入一个零，这使得该级的频率响应在幅度上增加20dB /十倍。零的频率位置也可以是可编程的，以允许每个级对特定频率贡献一定量的增益。每个阶段也可以被编程以确定用于降低高频噪声和串扰取消的极点的位置。

82. 发明授权

US07675326B1 Dynamically-adjustable differential output drivers 失效
标题翻译：动态可调差分输出驱动器
公开(公告)号：US07675326B1
公开(公告)日：2010-03-09
申请号：US12163709
申请日：2008-06-27
申请人： Mei Luo , Sergey Shumarayev , Wilson Wong , Chong H. Lee
发明人： Mei Luo , Sergey Shumarayev , Wilson Wong , Chong H. Lee
IPC分类号： H03K19/094
CPC分类号： H03K19/00369 , H03K19/01812 , H03K19/01837 , H03K19/018514 , H03K19/018585
摘要： Systems and methods are provided using dynamically adjustable differential output drivers. Integrated circuits such as programmable logic devices may be provided with adjustable differential output drivers for transmitting high-speed data to other integrated circuits. The peak-to-peak output voltage and common-mode voltage of the output drivers may be adjusted. Dynamic control circuitry may be used to control the settings of current sources, programmable resistors, and voltage source circuitry in the adjustable differential output driver automatically in real time. The adjustable components in the differential output driver may be adjusted by the dynamic control circuitry based on feedback information received from the integrated circuit to which the data is transmitted.
摘要翻译：使用动态可调差分输出驱动器提供系统和方法。诸如可编程逻辑器件的集成电路可以设置有用于将高速数据传输到其他集成电路的可调差分输出驱动器。可以调整输出驱动器的峰峰值输出电压和共模电压。动态控制电路可用于实时自动控制可调差分输出驱动器中的电流源，可编程电阻和电压源电路的设置。基于从发送数据的集成电路接收到的反馈信息，可以通过动态控制电路来调整差分输出驱动器中的可调节部件。

83. 发明授权

US07616657B2 Heterogeneous transceiver architecture for wide range programmability of programmable logic devices 有权
标题翻译：异构收发器架构，用于可编程逻辑器件的广泛可编程性
公开(公告)号：US07616657B2
公开(公告)日：2009-11-10
申请号：US11402417
申请日：2006-04-11
申请人： Sergey Shumarayev , Bill W Bereza , Chong H Lee , Rakesh H Patel , Wilson Wong
发明人： Sergey Shumarayev , Bill W Bereza , Chong H Lee , Rakesh H Patel , Wilson Wong
IPC分类号： H04J3/00
CPC分类号： H04L5/14 , H03K19/17744 , H04L27/00
摘要： High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.
摘要翻译：可编程逻辑器件（“PLD”）上的高速串行数据收发器电路包括一些能够以高达第一，相对较低的最大数据速率的数据速率工作的通道，以及能够以数据速率操作的其他通道达到第二个相对较高的最大数据速率。相对低速的通道由相对低速的锁相环（“PLL”）电路服务，并且具有通常用于处理以相对低的数据速率发送的数据所需的其他电路组件。相对高速的信道由相对高速的PLL服务，并且具有通常用于处理以相对高的数据速率传输的数据所需的其他电路部件。

84. 发明授权

US07602212B1 Flexible high-speed serial interface architectures for programmable integrated circuit devices 有权
标题翻译：用于可编程集成电路器件的灵活的高速串行接口架构
公开(公告)号：US07602212B1
公开(公告)日：2009-10-13
申请号：US11904003
申请日：2007-09-24
申请人： Allen Chan , Sergey Shumarayev , Wilson Wong
发明人： Allen Chan , Sergey Shumarayev , Wilson Wong
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： H03K19/17736 , H03K19/17732 , H03K19/17744
摘要： An integrated circuit (e.g., a programmable integrated circuit such as a programmable microcontroller, a programmable logic device, etc.) includes high-speed serial data signal interface channels, some of which include more circuitry that is dedicated to performing various high-speed serial interface functions than others of those channels have. To increase the flexibility with which such circuitry in a more feature-rich channel can be used, routing is provided for selectively allowing a less feature-rich channel to use certain dedicated circuitry of a more feature-rich channel that is not itself using all of its dedicated circuitry.
摘要翻译：集成电路（例如，可编程集成电路，例如可编程微控制器，可编程逻辑器件等）包括高速串行数据信号接口通道，其中一些包括更多专用于执行各种高速串行数据接口功能比其他那些通道有。为了增加可以使用更多功能丰富的信道中的这种电路的灵活性，提供路由选择性地允许较不富有特征的信道使用更多功能丰富的信道的某些专用电路，其不是本身使用全部其专用电路。

85. 发明申请

US20090154591A1 High-speed serial data signal transmitter driver circuitry 审中-公开
标题翻译：高速串行数据信号发射器驱动电路
公开(公告)号：US20090154591A1
公开(公告)日：2009-06-18
申请号：US12002540
申请日：2007-12-17
申请人： Wilson Wong , Allen Chan , Sergey Shumarayev , Weiqi Ding
发明人： Wilson Wong , Allen Chan , Sergey Shumarayev , Weiqi Ding
IPC分类号： H04L27/00
CPC分类号： H04L25/028
摘要： Transmitter driver circuitry for outputting a high-speed serial data signal (e.g., in the range of about 10 gigabits per second or higher) includes H-tree driver circuitry having only a main driver stage and a post-tap driver stage. At least one transistor in the H-tree driver circuitry is constructed and connected to provide electrostatic discharge protection. PMOS and NMOS current sources are used for the H-tree driver circuitry to enhance power supply noise rejection.
摘要翻译：用于输出高速串行数据信号（例如，在大约10吉比特每秒或更高的范围内）的发射器驱动器电路包括仅具有主驱动器级和抽头后驱动级的H树驱动器电路。 H树驱动器电路中的至少一个晶体管被构造和连接以提供静电放电保护。 PMOS和NMOS电流源用于H-tree驱动器电路，以增强电源噪声抑制。

86. 发明申请

US20090154542A1 High-speed serial data signal receiver circuitry 有权
标题翻译：高速串行数据信号接收电路
公开(公告)号：US20090154542A1
公开(公告)日：2009-06-18
申请号：US12002539
申请日：2007-12-17
申请人： Weiqi Ding , Mengchi Liu , Wilson Wong , Sergey Shumarayev
发明人： Weiqi Ding , Mengchi Liu , Wilson Wong , Sergey Shumarayev
IPC分类号： H03H7/30
CPC分类号： H04L25/03885 , H04L7/0054 , H04L25/03019 , H04L25/03878
摘要： Circuitry for receiving a high-speed serial data signal (e.g., having a bit rate in the range of about 10 Gpbs and higher) includes a two-stage, continuous-time, linear equalizer having only two serially connected stages. Phase detector circuitry may be provided for receiving the serial output of the equalizer and for converting successive pairs of bits in that output to successive parallel-form bit pairs. Further demultiplexing circuitry may be provided to demultiplex successive groups of the parallel-form bit pairs to final groups of parallel bits, which can be quite large in terms of number of bits (e.g., 64 parallel bits). Another aspect of the invention relates to multiplexer circuitry for efficiently going in the opposite direction from such relatively large groups of parallel data bits to a high-speed serial data output signal.
摘要翻译：用于接收高速串行数据信号（例如，具有在约10Gpbs及更高的范围内的比特率）的电路包括仅具有两个串联连接级的两级连续时间线性均衡器。可以提供相位检测器电路用于接收均衡器的串行输出，并将该输出中的连续比特对转换为连续并行形式的位对。可以提供进一步的解复用电路以将并行形式位对的连续组分解成最终并行位组，在位数（例如，64个并行位）方面可能相当大。本发明的另一方面涉及用于从相对大的并行数据比特组相对于高速串行数据输出信号有效地进行反向的多路复用器电路。

87. 发明授权

US07358883B1 Dynamic bias circuit 有权
标题翻译：动态偏置电路
公开(公告)号：US07358883B1
公开(公告)日：2008-04-15
申请号：US11470343
申请日：2006-09-06
申请人： Tin H. Lai , Wilson Wong , Sergey Shumarayev
发明人： Tin H. Lai , Wilson Wong , Sergey Shumarayev
IPC分类号： H03M1/66
CPC分类号： G11C7/12 , G11C7/1045 , H03M1/662
摘要： A bias circuit includes a digital to analog converter (D2A) generating an output representing a voltage level for tuning an analog signal. The D2A is coupled to a primary register frame that includes a plurality of register frames that are serially linked. The bias circuit includes a decoder also coupled to the primary register frame. An output enable logic module is also included. The output enable logic module determines when the primary register has a complete data set as the data is shifted into the primary register frame from a memory region that may be a ROM, RAM, soft IP of a PLD, an intelligent host or tester serial data input stream. A method for adjusting a signal through a bias circuit is also provided.
摘要翻译：偏置电路包括产生表示用于调谐模拟信号的电压电平的输出的数模转换器（D2A）。 D2A耦合到包括多个串行连接的寄存器帧的主寄存器帧。偏置电路包括还耦合到主寄存器框架的解码器。还包括一个输出使能逻辑模块。输出使能逻辑模块确定主寄存器何时具有完整数据集，因为数据从可能是ROM，RAM，PLD的软IP，智能主机或测试仪串行数据的存储器区域移入主寄存器帧输入流。还提供了一种通过偏置电路调整信号的方法。

88. 发明授权

US07245144B1 Adjustable differential input and output drivers 有权
标题翻译：可调差分输入和输出驱动器
公开(公告)号：US07245144B1
公开(公告)日：2007-07-17
申请号：US11169242
申请日：2005-06-27
申请人： Wilson Wong , Sergey Shumarayev
发明人： Wilson Wong , Sergey Shumarayev
IPC分类号： H03K17/16
CPC分类号： H03K19/018564 , H03F3/45928 , H03F2203/45078 , H03F2203/45082 , H03F2203/45101 , H03F2203/45134 , H03F2203/45138 , H03F2203/45154 , H03F2203/45222 , H03F2203/45541 , H03F2203/45566 , H03F2203/45626 , H03F2203/45681 , H03F2203/45686
摘要： Systems and methods are provided using common-mode-voltage bias circuitry to make common-mode-voltage adjustments to differential driver circuitry in integrated circuit differential communications links. Adjustable bias circuitry may be controlled using static and dynamic control signals. Dynamic control signals can be produced by core logic on a programmable logic device or other integrated circuit. Static control signals can be produced by programmable elements. Bias circuit adjustments made at one end of a differential link can be used to improve performance at either end of the link or can be used to improve power consumption or to balance power and performance considerations. The same integrated circuit design can be used in both AC-coupled and DC-coupled environments. The bias circuitry can be formed from an adjustable current source and adjustable resistor. The current source and adjustable resistors can be controlled by the same control signals.
摘要翻译：使用共模电压偏置电路提供系统和方法，以对集成电路差分通信链路中的差分驱动器电路进行共模电压调整。可调节的偏置电路可以使用静态和动态控制信号来控制。动态控制信号可以由可编程逻辑器件或其他集成电路上的核心逻辑产生。静态控制信号可以由可编程元件产生。差分链路一端进行的偏置电路调整可用于提高链路两端的性能，或者可用于提高功耗或平衡功率和性能考虑。同样的集成电路设计可用于交流耦合和直流耦合环境。偏置电路可以由可调电流源和可调电阻器形成。电流源和可调电阻可由相同的控制信号控制。

89. 发明申请

US20070014344A1 Programmable receiver equalization circuitry and methods 有权
标题翻译：可编程接收机均衡电路和方法
公开(公告)号：US20070014344A1
公开(公告)日：2007-01-18
申请号：US11182658
申请日：2005-07-14
申请人： Simardeep Maangat , Sergey Shumarayev , Wilson Wong , ThuNgoc Tran
发明人： Simardeep Maangat , Sergey Shumarayev , Wilson Wong , ThuNgoc Tran
IPC分类号： H03H7/30
CPC分类号： H04L25/03885 , H04B3/04 , H04L25/03019
摘要： Data signals transmitted over transmission media suffer from attenuation caused by the transmission media. Equalization circuitry may be provided to compensate for attenuation caused by the transmission media. Equalization circuitry may include multiple stages arranged in series to allow the frequency responses of the stages to aggregate together. Each stage may be programmable to insert a zero, which causes the frequency response of the stage to increase in magnitude by 20 dB/decade. The frequency location of the zero may also be programmable to allow each stage to contribute a certain amount of gain for a specific frequency. Each stage may also be programmable to determine the location of poles for reduction of high frequency noise and cross-talk cancellation.
摘要翻译：通过传输介质传输的数据信号遭受由传输介质引起的衰减。可以提供均衡电路以补偿由传输介质引起的衰减。均衡电路可以包括串联布置的多个级，以允许级的频率响应聚合在一起。每个级可以是可编程的，以插入一个零，这使得该级的频率响应在幅度上增加20dB /十倍。零的频率位置也可以是可编程的，以允许每个级对特定频率贡献一定量的增益。每个阶段也可以被编程以确定用于降低高频噪声和串扰取消的极点的位置。

90. 发明申请

US20060119382A1 Apparatus and methods for adjusting performance characteristics of programmable logic devices 审中-公开
标题翻译：用于调整可编程逻辑器件性能特性的装置和方法
公开(公告)号：US20060119382A1
公开(公告)日：2006-06-08
申请号：US11006420
申请日：2004-12-07
申请人： Sergey Shumarayev , Rakesh Patel
发明人： Sergey Shumarayev , Rakesh Patel
IPC分类号： H03K19/003
CPC分类号： H03K19/0016 , G06F17/5054 , G06F2217/84 , H01L2924/0002 , H03K19/00369 , H03K19/17732 , H03K19/17748 , H03K19/17784 , H03K19/17792 , H01L2924/00
摘要： A programmable logic device (PLD) includes a circuit that controls a supply voltage of at least a portion of the circuitry within the PLD (such as a block, a sub-block, or a region). The circuit also filters noise within the PLD. Controlling the supply voltage allows trading off various performance characteristics, such as speed and power consumption.
摘要翻译：可编程逻辑器件（PLD）包括控制PLD（例如块，子块或区域）内的电路的至少一部分的电源电压的电路。该电路还对PLD内的噪声进行滤波。控制电源电压可以消除各种性能特性，如速度和功耗。

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