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81. 发明授权

US09842036B2 Methods and apparatus for controlled recovery of error information between independently operable processors 有权
公开(公告)号：US09842036B2
公开(公告)日：2017-12-12
申请号：US14870923
申请日：2015-09-30
申请人： Apple Inc.
发明人： Karan Sanghi , Saurabh Garg , Vladislav Petkov , Haining Zhang
IPC分类号： G06F11/00 , G06F11/20 , G06F13/40 , G06F13/42
CPC分类号： G06F11/2028 , G06F13/4022 , G06F13/4221 , G06F2201/805
摘要： Methods and apparatus for controlled recovery of error information between two (or more) independently operable processors. The present disclosure provides solutions that preserve error information in the event of a fatal error, coordinate reset conditions between independently operable processors, and implement consistent frameworks for error information recovery across a range of potential fatal errors. In one exemplary embodiment, an applications processor (AP) and baseband processor (BB) implement an abort handler and power down handler sequence which enables error recovery over a wide range of crash scenarios. In one variant, assertion of signals between the AP and the BB enables the AP to reset the BB only after error recovery procedures have successfully completed.

82. 发明授权

US09798377B2 Methods and apparatus for recovering errors with an inter-processor communication link between independently operable processors 有权
公开(公告)号：US09798377B2
公开(公告)日：2017-10-24
申请号：US14879030
申请日：2015-10-08
申请人： Apple Inc.
发明人： Karan Sanghi , Saurabh Garg , Haining Zhang
IPC分类号： G06F11/00 , G06F1/32 , G06F13/42 , G06F9/44 , G06F11/14
CPC分类号： G06F1/3293 , G06F1/3228 , G06F1/3243 , G06F1/3287 , G06F9/4403 , G06F9/4405 , G06F9/4411 , G06F11/1417 , G06F11/1471 , G06F11/1474 , G06F13/4282 , G06F2201/805 , G06F2201/87 , Y02D10/122 , Y02D10/14 , Y02D10/151 , Y02D10/152 , Y02D10/171
摘要： Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.

83. 发明申请

US20170286322A1 MEMORY ACCESS PROTECTION APPARATUS AND METHODS 审中-公开
公开(公告)号：US20170286322A1
公开(公告)日：2017-10-05
申请号：US15271102
申请日：2016-09-20
申请人： Apple Inc.
发明人： Saurabh Garg , Karan Sanghi , Vladislav Petkov , Haining Zhang
IPC分类号： G06F12/14 , G06F21/62
CPC分类号： G06F12/1441 , G06F12/1081 , G06F2212/1052
摘要： Methods and apparatus for registering and handling access violations of host memory. In one embodiment, a peripheral processor receives one or more window registers defining an extent of address space accessible from a host processor; responsive to an attempt to access an extent of address space outside of the extent of accessible address space, generates an error message; stores the error message within a violation register; and resumes operation of the peripheral processor upon clearance of the stored error message.

84. 发明申请

US20160364350A1 METHODS AND APPARATUS FOR SYNCHRONIZING UPLINK AND DOWNLINK TRANSACTIONS ON AN INTER-DEVICE COMMUNICATION LINK 审中-公开
标题翻译：用于在设备间通信链路上同步上行链路和下行链路交换的方法和装置
公开(公告)号：US20160364350A1
公开(公告)日：2016-12-15
申请号：US15011291
申请日：2016-01-29
申请人： Apple Inc.
发明人： Karan Sanghi , Vladislav Petkov , Radha Kumar Pulyala , Saurabh Garg , Haining Zhang
IPC分类号： G06F13/28 , G06F13/40
CPC分类号： G06F13/28 , G06F13/4027 , Y02D10/14 , Y02D10/151
摘要： Methods and apparatus for a synchronized multi-directional transfer on an inter-processor communication (IPC) link. In one embodiment, the synchronized multi-directional transfer utilizes one or more buffers which are configured to accumulate data during a first state. The one or more buffers are further configured to transfer the accumulated data during a second state. Data is accumulated during a low power state where one or more processors are inactive, and the data transfer occurs during an operational state where the processors are active. Additionally, in some variants, the data transfer may be performed for currently available transfer resources, and halted until additional transfer resources are made available. In still other variants, one or more of the independently operable processors may execute traffic monitoring processes so as to optimize data throughput of the IPC link.
摘要翻译：在处理器间通信（IPC）链路上进行同步多方向传输的方法和装置。在一个实施例中，同步多向传输利用被配置为在第一状态期间累积数据的一个或多个缓冲器。一个或多个缓冲器还被配置为在第二状态期间传送累积的数据。在一个或多个处理器不活动的低功率状态期间，数据被累积，并且数据传输在处理器处于活动状态的操作状态期间发生。此外，在一些变型中，可以对当前可用的传输资源执行数据传输，并且停止直到额外的传输资源可用。在其他变型中，一个或多个可独立操作的处理器可以执行流量监控过程，以便优化IPC链路的数据吞吐量。

85. 发明申请

US20160103689A1 METHODS AND APPARATUS FOR RUNNING AND BOOTING AN INTER-PROCESSOR COMMUNICATION LINK BETWEEN INDEPENDENTLY OPERABLE PROCESSORS 审中-公开
标题翻译：运行和启动独立运行处理器之间的处理器间通信链路的方法和装置
公开(公告)号：US20160103689A1
公开(公告)日：2016-04-14
申请号：US14879024
申请日：2015-10-08
申请人： Apple Inc.
发明人： Karan Sanghi , Saurabh Garg , Haining Zhang
IPC分类号： G06F9/44 , G06F13/42
CPC分类号： G06F1/3293 , G06F1/3228 , G06F1/3243 , G06F1/3287 , G06F9/4403 , G06F9/4405 , G06F9/4411 , G06F11/1417 , G06F11/1471 , G06F11/1474 , G06F13/4282 , G06F2201/805 , G06F2201/87 , Y02D10/122 , Y02D10/14 , Y02D10/151 , Y02D10/152 , Y02D10/171
摘要： Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.
摘要翻译：两个（或多个）可独立操作的处理器之间的处理器间通信（IPC）链接的方法和装置。在一个方面，IPC协议基于用于运行时处理的“共享”存储器接口（即，独立可操作的处理器每个共享（虚拟或物理上）公共存储器接口）。在另一方面，IPC通信链路被配置为支持在引导序列期间使用的主机驱动的引导协议，以在外围设备和主处理器之间建立基本通信路径。本文描述的各种其他实施例包括睡眠过程（如针对主机和外围处理器分别定义的）和错误处理。

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