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81. 发明授权

US06977910B1 Power control with space time transmit diversity 有权
标题翻译：功率控制与时空发射分集
公开(公告)号：US06977910B1
公开(公告)日：2005-12-20
申请号：US09224401
申请日：1998-12-31
申请人： Srinath Hosur , Anand G. Dabak
发明人： Srinath Hosur , Anand G. Dabak
IPC分类号： H04B1/00 , H04B1/02 , H04B1/707 , H04B7/005 , H04B7/185 , H04B7/216
CPC分类号： H04B7/0669 , H04B1/712 , H04B2201/70707 , H04W52/08 , H04W52/241 , H04W52/245 , H04W52/42
摘要： A circuit is designed with a measurement circuit (432). The measurement circuit is coupled to receive a first input signal (903) from a first antenna (128) of a transmitter and coupled to receive a second input signal (913) from a second antenna (130) of the transmitter. Each of the first and second signals is transmitted at a first time. The measurement circuit produces an output signal corresponding to a magnitude of the first and second signals. A control circuit (430) is coupled to receive the output signal and a reference signal. The control circuit is arranged to produce a control signal at a second time in response to a comparison of the output signal and the reference signal.
摘要翻译：电路设计有测量电路（432）。测量电路被耦合以从发射机的第一天线（128）接收第一输入信号（903），并被耦合以从发射机的第二天线（130）接收第二输入信号（913）。第一和第二信号中的每一个在第一时间被发送。测量电路产生对应于第一和第二信号的幅度的输出信号。控制电路（430）被耦合以接收输出信号和参考信号。控制电路被布置成响应于输出信号和参考信号的比较而在第二时间产生控制信号。

82. 发明申请

US20050113041A1 Frequency-domain subchannel transmit antenna selection and power pouring for multi-antenna transmission 有权
标题翻译：用于多天线传输的频域子信道发射天线选择和电力倾倒
公开(公告)号：US20050113041A1
公开(公告)日：2005-05-26
申请号：US10723215
申请日：2003-11-26
申请人： Michael Polley , Donald Shaver , Srinath Hosur , Eko Onggosanusi , Muhammad Ikram , Anand Dabak
发明人： Michael Polley , Donald Shaver , Srinath Hosur , Eko Onggosanusi , Muhammad Ikram , Anand Dabak
IPC分类号： H04B7/005 , H04B1/02
CPC分类号： H04W52/42
摘要： A system comprises a wireless device that communicates across a spectrum having a plurality of sub-channels. The wireless device comprises a plurality of antennas through which the wireless device communicates with another wireless device, wherein each antenna communicates with the other wireless device via an associated communication pathway. The wireless device further comprises sub-channel power analysis logic coupled to the antennas and adapted to determine which communication pathway has the highest communication quality on a sub-channel by sub-channel basis. The wireless device still further comprises diversity selection logic coupled to the sub-channel power analysis logic and adapted to determine a weighting vector for an associated antenna based on the communication quality, wherein the weighting vector specifies a relative transmission power for each sub-channel for the associated antenna.
摘要翻译：一种系统包括在具有多个子信道的频谱上进行通信的无线设备。无线设备包括多个天线，无线设备通过多个天线与另一无线设备通信，其中每个天线经由相关联的通信路径与另一无线设备进行通信。无线设备还包括耦合到天线的子信道功率分析逻辑，并且适于通过子信道来确定子信道上哪个通信路径具有最高通信质量。无线设备还包括耦合到子信道功率分析逻辑的分集选择逻辑，并且适于基于通信质量来确定相关天线的加权矢量，其中加权向量规定每个子信道的相对发射功率，用于相关天线。

83. 发明申请

US20050044472A1 Wireless access modem having downstream channel resynchronization method 有权
标题翻译：具有下行信道重新同步方式的无线接入调制解调器
公开(公告)号：US20050044472A1
公开(公告)日：2005-02-24
申请号：US10643119
申请日：2003-08-18
申请人： Xiaolin Lu , Srinath Hosur , Manish Goel , Michael Polley
发明人： Xiaolin Lu , Srinath Hosur , Manish Goel , Michael Polley
IPC分类号： H03M13/00 , H04B1/38 , H04L7/04 , H04L7/10
CPC分类号： H04W56/009 , H04L7/048 , H04L7/10 , H04W24/00 , H04W74/00
摘要： A resynchronization method for use in a data communication system having a first device configured to transmit data at a symbol rate to a second device. The second device includes a Reed Solomon (RS) decoder having a RS lock indicator and a Moving Picture Experts Group (MPEG) Protocol Interface (MPI) having a MPI lock indicator, wherein the RS and the MPI lock indicators are monitored. Four different states, defined by the values of the RS and MPI lock indicators, determine whether the data communication system will wait for the RS decoder and the MPI hardware block to resynchronize, whether an intermediate-subset of the channel acquisition algorithm is performed or whether the entire channel acquisition algorithm is performed. The method for resynchronization described herein recovers synchronization within a predetermined time without the layers above the physical link layer having knowledge.
摘要翻译：一种用于具有第一设备的数据通信系统中的再同步方法，该第一设备被配置为以符号速率向第二设备发送数据。第二装置包括具有RS锁定指示器的里德所罗门（RS）解码器和具有MPI锁定指示器的运动图像专家组（MPEG）协议接口（MPI），其中监测RS和MPI锁定指示符。由RS和MPI锁指示符的值定义的四种不同状态确定数据通信系统是否将等待RS解码器和MPI硬件块重新同步，无论是执行信道获取算法的中间子集还是执行执行整个信道获取算法。本文所述的用于重新同步的方法在预定时间内恢复同步，而不具有物理链路层之上的层具有知识。

84. 发明申请

US20050018646A1 Multistage PN code acquisition circuit and method 有权
标题翻译：多级PN码采集电路及方法
公开(公告)号：US20050018646A1
公开(公告)日：2005-01-27
申请号：US10918839
申请日：2004-08-13
申请人： Sundararajan Sriram , Srinath Hosur
发明人： Sundararajan Sriram , Srinath Hosur
IPC分类号： H04B1/707 , H04K1/00
CPC分类号： H04B1/70752 , H04B1/70735 , H04B1/7077 , H04B1/7093 , H04B2201/70702 , H04B2201/70707
摘要： A circuit for detecting a serial signal comprises a first circuit (400) coupled to receive the serial signal (200) during a predetermined plurality of time periods of substantially equal duration. The first circuit is coupled to receive a first code (414). The first circuit is arranged to compare a part of the serial signal corresponding to each time period of the plurality of time periods to the first code, thereby producing a match signal. The first circuit accumulates the match signal from each of the each time period of the plurality of time periods.
摘要翻译：用于检测串行信号的电路包括第一电路（400），该第一电路被耦合以在基本相等的持续时间的预定多个时间段内接收串行信号（200）。第一电路被耦合以接收第一代码（414）。第一电路被布置为将与多个时间段的每个时间段相对应的串行信号的一部分与第一代码进行比较，从而产生匹配信号。第一电路从多个时间段的每个时间段的每一个累加匹配信号。

85. 发明授权

US08923362B2 Wireless communications system with secondary synchronization code based on values in primary synchronization code 有权
公开(公告)号：US08923362B2
公开(公告)日：2014-12-30
申请号：US13403201
申请日：2012-02-23
申请人： Anand G. Dabak , Sundararajan Sriram , Srinath Hosur
发明人： Anand G. Dabak , Sundararajan Sriram , Srinath Hosur
IPC分类号： H04B1/69 , H04B1/707 , H04B1/713 , H04B1/7083 , H04B1/7073 , H04J13/00 , H04J13/12
CPC分类号： H04B1/7083 , H04B1/70735 , H04J13/00 , H04J13/12
摘要： A wireless communication system. The system comprises transmitter circuitry (BST1), the transmitter circuitry comprising encoder circuitry (50) for transmitting a plurality of frames (FR). Each of the plurality of frames comprises a primary synchronization code (PCS) and a second synchronization code (SSC). The encoder circuitry comprises of circuitry (501) for providing the primary synchronization code in response to a first sequence (32). The encoder circuitry further comprises circuitry (502) for providing the secondary synchronization code in response to a second sequence (54) and a third sequence (56). The second sequence is selected from a plurality of sequences. Each of the plurality of sequences is orthogonal with respect to all other sequences. The third sequence is a subset of bits from the first sequence.

86. 发明授权

US08681834B2 Wireless communications system with secondary synchronization code based on values in primary synchronization code 有权
标题翻译：基于主同步码中的值的无线通信系统具有辅同步码
公开(公告)号：US08681834B2
公开(公告)日：2014-03-25
申请号：US13403236
申请日：2012-02-23
申请人： Anand G. Dabak , Sundararajan Sriram , Srinath Hosur
发明人： Anand G. Dabak , Sundararajan Sriram , Srinath Hosur
IPC分类号： H04B1/69 , H04B1/707 , H04B1/713
CPC分类号： H04B1/7083 , H04B1/70735 , H04J13/00 , H04J13/12
摘要： A wireless communication system. The system comprises transmitter circuitry (BST1), the transmitter circuitry comprising encoder circuitry (50) for transmitting a plurality of frames (FR). Each of the plurality of frames comprises a primary synchronization code (PCS) and a second synchronization code (SSC). The encoder circuitry comprises of circuitry (501) for providing the primary synchronization code in response to a first sequence (32). The encoder circuitry further comprises circuitry (502) for providing the secondary synchronization code in response to a second sequence (54) and a third sequence (56). The second sequence is selected from a plurality of sequences. Each of the plurality of sequences is orthogonal with respect to all other sequences. The third sequence is a subset of bits from the first sequence.
摘要翻译：无线通信系统。该系统包括发射机电路（BST1），该发射机电路包括用于传输多个帧（FR）的编码器电路（50）。多个帧中的每一个包括主同步码（PCS）和第二同步码（SSC）。编码器电路包括用于响应于第一序列（32）提供主同步码的电路（501）。编码器电路还包括用于响应于第二序列（54）和第三序列（56）提供辅助同步码的电路（502）。第二序列从多个序列中选择。多个序列中的每一个相对于所有其他序列是正交的。第三个序列是来自第一个序列的比特的子集。

87. 发明授权

US08472569B2 Fine symbol timing estimation 有权
标题翻译：精细符号定时估计
公开(公告)号：US08472569B2
公开(公告)日：2013-06-25
申请号：US12961271
申请日：2010-12-06
申请人： June Chul Roh , Srinath Hosur , Timothy M. Schmidl
发明人： June Chul Roh , Srinath Hosur , Timothy M. Schmidl
IPC分类号： H03D1/00 , H04L27/06
CPC分类号： H04L27/205 , H04L27/2335
摘要： Systems and methods for fine symbol timing estimation are disclosed herein. In one embodiment, a wireless receiver includes a differential detector, a correlator, a coarse symbol timing estimator, and a fine symbol timing estimator. The differential detector is configured to detect phase differences in a received preamble signal modulated using differential phase shift keying. The correlator is configured to correlate symbol values output by the differential detector against a reference sequence. The coarse symbol timing estimator is configured to generate a coarse symbol timing estimate, and to generate a coarse timing sample symbol index value corresponding to the coarse symbol timing estimate. The fine symbol timing estimator is configured to generate a fine symbol timing estimate that is more accurate than the coarse symbol timing estimate based on the coarse timing sample symbol index value and correlation samples at index values preceding and succeeding the coarse timing sample index value.
摘要翻译：本文公开了用于精细符号定时估计的系统和方法。在一个实施例中，无线接收机包括差分检测器，相关器，粗略符号定时估计器和精细符号定时估计器。差分检测器被配置为检测使用差分相移键控调制的接收前导信号中的相位差。相关器被配置为将由差分检测器输出的符号值与参考序列相关联。粗略符号定时估计器被配置为产生粗略符号定时估计，并且生成与粗略符号定时估计对应的粗定时采样符号索引值。精细符号定时估计器被配置为基于粗略定时样本符号索引值和在粗略定时样本索引值之前和之后的索引值处的相关样本，生成比粗略符号定时估计更精确的精细符号定时估计。

88. 发明授权

US08472437B2 Wireless chip-to-chip switching 有权
标题翻译：无线芯片到芯片切换
公开(公告)号：US08472437B2
公开(公告)日：2013-06-25
申请号：US13026777
申请日：2011-02-14
申请人： Nirmal Chindhu Warke , Srinath Hosur , Martin J. Izzard , Siraj Akhtar , Baher S. Haroun , Marco Corsi
发明人： Nirmal Chindhu Warke , Srinath Hosur , Martin J. Izzard , Siraj Akhtar , Baher S. Haroun , Marco Corsi
IPC分类号： H04L12/50 , H04L12/28 , H04L12/56 , H04Q11/00 , H04B5/00 , H04B7/00
CPC分类号： H04W40/00 , H01Q3/26 , H01Q9/20 , H01Q21/0006 , H01Q21/0037 , H04B7/0617 , H04B17/336 , H04L45/74 , H04L49/3009 , H04L49/40 , H04W40/06 , H04W40/12 , Y02D70/00 , Y02D70/166 , Y02D70/322 , Y02D70/34
摘要： Embodiments of the invention provide a system and method for chip to chip communications in electronic circuits. A router or switch receives data packets at input port ASICs. A routing table on the input port ASIC or on a routing ASIC is used to identify a destination port ASIC based upon header information in the data packet. The data packet is transmitted from the input port ASIC to the destination port ASIC using millimeter wave signals that are transmitted across a waveguide or a wireless interface.
摘要翻译：本发明的实施例提供了一种用于电子电路中芯片到芯片通信的系统和方法。路由器或交换机在输入端口ASIC处接收数据包。输入端口ASIC或路由ASIC上的路由表用于根据数据包中的报头信息识别目标端口ASIC。使用在波导或无线接口上传输的毫米波信号，将数据分组从输入端口ASIC发送到目标端口ASIC。

89. 发明申请

US20130058329A1 WIRELESS ROUTER SYSTEM 有权
标题翻译：无线路由器系统
公开(公告)号：US20130058329A1
公开(公告)日：2013-03-07
申请号：US13226133
申请日：2011-09-06
申请人： Nirmal C. Warke , Brad Kramer , Hassan Ali , Swaminathan Sankaran , Baher Haroun , Srinath Hosur , Martin J. Izzard
发明人： Nirmal C. Warke , Brad Kramer , Hassan Ali , Swaminathan Sankaran , Baher Haroun , Srinath Hosur , Martin J. Izzard
IPC分类号： H04L12/50
CPC分类号： H04L12/50 , G06F13/4022 , Y02D10/14 , Y02D10/151
摘要： Conventional routers employ a wired backplane that employs “long reach” serializer/deserializer (SerDes) links, but this type of architecture is complicated, costly, and uses a considerable amount of power. To address some of these issues, a new wireless backplane architecture is provided here. This wireless backplane employs direct millimeter wave links between line cards that replaces the convention, wired switching fabric.
摘要翻译：常规路由器采用使用长距离串行器/解串器（SerDes）链路的有线背板，但是这种类型的架构是复杂的，昂贵的并且使用相当大的功率。为了解决其中的一些问题，这里提供了一种新的无线背板架构。该无线背板在线路卡之间采用直接毫米波链接，取代了常规，有线交换结构。

90. 发明授权

US08144747B2 Primary and secondary synchronization codes from first, second, third sequences 有权
标题翻译：来自第一，第二和第三序列的主和次同步码
公开(公告)号：US08144747B2
公开(公告)日：2012-03-27
申请号：US12949413
申请日：2010-11-18
申请人： Anand G. Dabak , Sundararajan Sriram , Srinath Hosur
发明人： Anand G. Dabak , Sundararajan Sriram , Srinath Hosur
IPC分类号： H04B1/69 , H04B1/707 , H04B1/713
CPC分类号： H04B1/7083 , H04B1/70735 , H04J13/00 , H04J13/12
摘要： A wireless communication system. The system comprises transmitter circuitry (BST1), the transmitter circuitry comprising encoder circuitry (50) for transmitting a plurality of frames (FR). Each of the plurality of frames comprises a primary synchronization code (PCS) and a secondary synchronization code (SSC). The encoder circuitry comprises of circuitry (501) for providing the primary synchronization code in response to a first sequence (32). The encoder circuitry further comprises circuitry (502) for providing the secondary synchronization code in response to a second sequence (54) and a third sequence (56). The second sequence is selected from a plurality of sequences. Each of the plurality of sequences is orthogonal with respect to all other sequences in the plurality of sequences. The third sequence comprises a subset of bits from the first sequence.
摘要翻译：无线通信系统。该系统包括发射机电路（BST1），该发射机电路包括用于传输多个帧（FR）的编码器电路（50）。多个帧中的每一个包括主同步码（PCS）和辅同步码（SSC）。编码器电路包括用于响应于第一序列（32）提供主同步码的电路（501）。编码器电路还包括用于响应于第二序列（54）和第三序列（56）提供辅助同步码的电路（502）。第二序列从多个序列中选择。多个序列中的每一个相对于多个序列中的所有其他序列是正交的。第三序列包括来自第一序列的比特的子集。

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