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81. 发明授权

US06895416B2 Checkpointing filesystem 失效
标题翻译：检查点文件系统
公开(公告)号：US06895416B2
公开(公告)日：2005-05-17
申请号：US10258515
申请日：2002-02-25
申请人： Alan G. Gara , Mark E. Giampapa , Burkhard D. Steinmacher-Burow
发明人： Alan G. Gara , Mark E. Giampapa , Burkhard D. Steinmacher-Burow
IPC分类号： G06F7/00 , G06F17/00
CPC分类号： G06F11/1438 , Y10S707/99953 , Y10S707/99955
摘要： The present in invention is directed to a checkpointing filesystem of a distributed-memory parallel supercomputer comprising a node that accesses user data on the filesystem, the filesystem comprising an interface that is associated with a disk for storing the user data. The checkpointing filesystem provides for taking and checkpoint of the filesystem and rolling back to a previously taken checkpoint, as well as for writing user data to and deleting user data from the checkpointing filesystem. The checkpointing filesystem provides a recently written file allocation table (WFAT) for maintaining information regarding the user data written since a previously taken checkpoint and a recently deleted file allocation table (DFAT) for maintaining information regarding user data deleted from since the previously taken checkpoint, both of which are utilized by the checkpointing filesystem to take a checkpoint of the filesystem and rollback the filesystem to a previously taken checkpoint, as well as to write and delete user data from the checkpointing filesystem.
摘要翻译：本发明涉及一种分布式存储器并行超级计算机的检查点文件系统，其包括访问文件系统上的用户数据的节点，该文件系统包括与用于存储用户数据的盘相关联的接口。检查点文件系统提供文件系统的获取和检查点，并回滚到先前执行的检查点，以及从检查点文件系统向用户数据写入和删除用户数据。检查点文件系统提供最近写入的文件分配表（WFAT），用于维护关于自先前检查点以来写入的用户数据的信息，以及用于维护关于从先前检查点以来删除的用户数据的信息的最近删除的文件分配表（DFAT）这两个都由检查点文件系统用于采取文件系统的检查点并将文件系统回滚到先前执行的检查点，以及从检查点文件系统写入和删除用户数据。

82. 发明授权

US09857858B2 Managing power consumption and performance of computing systems 有权
公开(公告)号：US09857858B2
公开(公告)日：2018-01-02
申请号：US13976817
申请日：2012-05-17
申请人： Devadatta V. Bodas , John H. Crawford , Alan G. Gara
发明人： Devadatta V. Bodas , John H. Crawford , Alan G. Gara
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3206 , G06F1/3209 , G06F1/3234
摘要： A method and system for managing power consumption and performance of computing systems are described herein. The method includes monitoring an overall power consumption of the computing systems to determine whether the overall power consumption is above or below an overall power consumption limit, and monitoring a performance of each computing system to determine whether the performance is within a performance tolerance. The method further includes adjusting the power consumption limits for the computing systems or the performances of the computing systems such that the overall power consumption is below the overall power consumption limit and the performance of each computing system is within the performance tolerance.

83. 发明授权

US08627010B2 Write-through cache optimized for dependence-free parallel regions 有权
标题翻译：针对无依赖并行区域优化的直写缓存
公开(公告)号：US08627010B2
公开(公告)日：2014-01-07
申请号：US13604349
申请日：2012-09-05
申请人： Alexandre E. Eichenberger , Alan G. Gara , Martin Ohmacht , Vijayalakshmi Srinivasan
发明人： Alexandre E. Eichenberger , Alan G. Gara , Martin Ohmacht , Vijayalakshmi Srinivasan
IPC分类号： G06F12/00
CPC分类号： G06F12/0837
摘要： An apparatus and computer program product for improving performance of a parallel computing system. A first hardware local cache controller associated with a first local cache memory device of a first processor detects an occurrence of a false sharing of a first cache line by a second processor running the program code and allows the false sharing of the first cache line by the second processor. The false sharing of the first cache line occurs upon updating a first portion of the first cache line in the first local cache memory device by the first hardware local cache controller and subsequent updating a second portion of the first cache line in a second local cache memory device by a second hardware local cache controller.
摘要翻译：一种用于提高并行计算系统性能的设备和计算机程序产品。与第一处理器的第一本地高速缓冲存储器设备相关联的第一硬件本地高速缓存控制器通过运行程序代码的第二处理器来检测第一高速缓存行的虚假共享的发生，并允许第一高速缓存行的错误共享由第二处理器。当由第一硬件本地高速缓存控制器更新第一本地高速缓存存储器设备中的第一高速缓存行的第一部分并且随后在第二本地高速缓冲存储器中更新第一高速缓存行的第二部分时，发生第一高速缓存行的错误共享设备由第二硬件本地缓存控制器。

84. 发明授权

US07603524B2 Method and apparatus for filtering snoop requests using multiple snoop caches 有权
标题翻译：用于使用多个监听高速缓存来过滤窥探请求的方法和装置
公开(公告)号：US07603524B2
公开(公告)日：2009-10-13
申请号：US12042958
申请日：2008-03-05
申请人： Matthias A. Blumrich , Alan G. Gara , Valentina Salapura
发明人： Matthias A. Blumrich , Alan G. Gara , Valentina Salapura
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0831 , G06F12/0822 , G06F2212/507 , Y02D10/13
摘要： A method and apparatus for implementing a snoop filter unit associated with a single processor in a multiprocessor system. The snoop filter unit has a plurality of ports, each port receiving snoop requests from exactly one dedicated source. Associated with each port is a snoop cache filter that processes each snoop cache request and records addresses of the most recent snoop requests for exactly one source. The snoop cache filter uses vector encoding to record the occurrence of snoop requests for a sequence of consecutive cache lines. All addresses of snoop requests are added to the snoop cache unless a received snoop cache request matches an entry present in the associated snoop cache, in which case the snoop request is discarded. Otherwise, the associated snoop cache request is enqueued for forwarding to the single processor. Information from all snoop cache filters assigned to all ports in the snoop filter unit are removed in the case that data corresponding to any one of the memory addresses contained in snoop cache filter is loaded in the cache hierarchy of the processor the snoop cache filter is assigned to.
摘要翻译：一种用于在多处理器系统中实现与单个处理器相关联的窥探滤波器单元的方法和装置。监听过滤器单元具有多个端口，每个端口接收来自正好一个专用源的窥探请求。与每个端口相关联的是一个侦听缓存过滤器，用于处理每个侦听缓存请求，并记录最近一次侦听请求的地址。监听高速缓存过滤器使用向量编码来记录连续高速缓存行序列的窥探请求的发生。侦听请求的所有地址都将添加到侦听缓存中，除非接收到的侦听缓存请求与相关侦听缓存中存在的条目匹配，在这种情况下，侦听请求将被丢弃。否则，相关联的侦听缓存请求被排入队列以转发到单个处理器。在分配给窥探过滤器单元中的所有端口的所有侦听缓存过滤器中的信息将被删除，因为与侦听高速缓存过滤器中包含的任何一个存储器地址相对应的数据被加载到处理器的高速缓存层次结构中，该侦听缓存过滤器被分配至。

85. 发明申请

US20090116611A1 SPACE AND POWER EFFICIENT HYBRID COUNTERS ARRAY 失效
标题翻译：空间和功率有效的混合计数器阵列
公开(公告)号：US20090116611A1
公开(公告)日：2009-05-07
申请号：US12120416
申请日：2008-05-14
申请人： Alan G. Gara , Valentina Salapura
发明人： Alan G. Gara , Valentina Salapura
IPC分类号： G06M3/00
CPC分类号： H03K21/026
摘要： A hybrid counter array device for counting events. The hybrid counter array includes a first counter portion comprising N counter devices, each counter device for receiving signals representing occurrences of events from an event source and providing a first count value corresponding to a lower order bits of the hybrid counter array. The hybrid counter array includes a second counter portion comprising a memory array device having N addressable memory locations in correspondence with the N counter devices, each addressable memory location for storing a second count value representing higher order bits of the hybrid counter array. A control device monitors each of the N counter devices of the first counter portion and initiates updating a value of a corresponding second count value stored at the corresponding addressable memory location in the second counter portion. Thus, a combination of the first and second count values provide an instantaneous measure of number of events received.
摘要翻译：用于计数事件的混合计数器阵列装置。混合计数器阵列包括包括N个计数器装置的第一计数器部分，每个计数器装置用于接收表示来自事件源的事件发生的信号，并提供对应于混合计数器阵列的较低位的第一计数值。混合计数器阵列包括第二计数器部分，其包括具有与N个计数器装置对应的N个可寻址存储器位置的存储器阵列器件，每个可寻址存储器位置用于存储表示混合计数器阵列的较高阶位的第二计数值。控制装置监视第一计数器部分的N个计数器装置中的每一个，并且启动更新存储在第二计数器部分中相应的可寻址存储器位置处的对应的第二计数值的值。因此，第一和第二计数值的组合提供了接收事件数量的瞬时量度。

86. 发明申请

US20090077571A1 METHOD AND APPARATUS FOR EFFICIENT PERFORMANCE MONITORING OF A LARGE NUMBER OF SIMULTANEOUS EVENTS 有权
标题翻译：大量同时活动的有效执行监测方法和装置
公开(公告)号：US20090077571A1
公开(公告)日：2009-03-19
申请号：US12324254
申请日：2008-11-26
申请人： Alan G. Gara , Michael K. Gschwind , Valentina Salapura
发明人： Alan G. Gara , Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F3/00
CPC分类号： G06F11/348 , Y02D10/34
摘要： A system for monitoring a large number of simultaneous events implements a hybrid counter array device having a first counter portion comprising counter devices, each counter device for receiving signals representing occurrences of events from an event source and providing a first count value corresponding to a lower order bits of the hybrid counter array. A second counter portion comprises a memory array device having addressable memory locations in correspondence with the counter devices, each addressable memory location for storing a second count value representing higher order bits. A control device monitors each of the counter devices and initiates updating a value of a corresponding second count value stored at the corresponding addressable memory location. The system includes interrupt pre-indication for providing fast interrupt trigger to a processor device when a count value related to an event equals a threshold value. A data transfer sub-system additionally enables one or more of: read access or write access to both the count values in the first and second counter portions over a narrow bus, the read/write access for purposes of initializing and determining status of the count values for a monitored event type in response to a processor device request.
摘要翻译：一种用于监视大量同时事件的系统实现了具有包括计数器装置的第一计数器部分的混合计数器阵列装置，每个计数器装置用于接收表示从事件源发生的事件的信号，并提供对应于较低次序的第一计数值混合计数器阵列的位。第二计数器部分包括具有与计数器装置对应的可寻址存储器位置的存储器阵列器件，每个可寻址存储器位置用于存储表示较高阶位的第二计数值。控制装置监视每个计数器装置并且启动更新存储在相应的可寻址存储器位置处的对应的第二计数值的值。当与事件相关的计数值等于阈值时，该系统包括用于向处理器设备提供快速中断触发的中断预指示。数据传输子系统另外启用以下一个或多个：通过窄总线对第一和第二计数器部分中的计数值进行读访问或写入访问，用于初始化和确定计数状态的读/写访问响应于处理器设备请求的被监视事件类型的值。

87. 发明授权

US07404041B2 Low complexity speculative multithreading system based on unmodified microprocessor core 失效
标题翻译：基于未修改的微处理器核心的低复杂度推测性多线程系统
公开(公告)号：US07404041B2
公开(公告)日：2008-07-22
申请号：US11351830
申请日：2006-02-10
申请人： Alan G. Gara , Michael K. Gschwind , Valentina Salapura
发明人： Alan G. Gara , Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F9/3828 , G06F9/3842 , G06F9/3851 , G06F12/0815 , G06F2212/507
摘要： A system, method and computer program product for supporting thread level speculative execution in a computing environment having multiple processing units adapted for concurrent execution of threads in speculative and non-speculative modes. Each processing unit includes a cache memory hierarchy of caches operatively connected therewith. The apparatus includes an additional cache level local to each processing unit for use only in a thread level speculation mode, each additional cache for storing speculative results and status associated with its associated processor when handling speculative threads. The additional local cache level at each processing unit are interconnected so that speculative values and control data may be forwarded between parallel executing threads. A control implementation is provided that enables speculative coherence between speculative threads executing in the computing environment.
摘要翻译：一种用于在具有多个处理单元的计算环境中支持线程级推测性执行的系统，方法和计算机程序产品，该处理单元适于以推测和非推测模式并行执行线程。每个处理单元包括与其可操作地连接的高速缓存的高速缓冲存储器层级。该装置包括仅在线程级推测模式中使用的每个处理单元本地的附加高速缓存级别，每个附加高速缓存用于存储推测结果以及处理推测性线程时与其相关联的处理器相关联的状态。在每个处理单元处的附加本地高速缓存级别互连，使得推测值和控制数据可以在并行执行线程之间转发。提供了一种控制实现，其实现在计算环境中执行的推测线程之间的推测性一致性。

88. 发明申请

US20080126634A1 Method and apparatus for updating wide storage array over a narrow bus 有权
标题翻译：用于在窄总线上更新宽存储阵列的方法和装置
公开(公告)号：US20080126634A1
公开(公告)日：2008-05-29
申请号：US11507306
申请日：2006-08-21
申请人： Alan G. Gara , Michael K. Gschwind , Valentina Salapura
发明人： Alan G. Gara , Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F13/38
CPC分类号： G06F13/4018 , Y02D10/14 , Y02D10/151
摘要： A method and apparatus for transferring wide data (e.g., n bits) from a narrow bus (m bits, where m
摘要翻译：一种用于从窄总线（m位，其中m

89. 发明授权

US07877759B2 System for efficient performance monitoring of a large number of simultaneous events 有权
标题翻译：系统用于高效率监控大量同时发生的事件
公开(公告)号：US07877759B2
公开(公告)日：2011-01-25
申请号：US12324254
申请日：2008-11-26
申请人： Alan G. Gara , Michael K. Gschwind , Valentina Salapura
发明人： Alan G. Gara , Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F3/00 , G06F9/44 , G06F9/46 , G06F13/00
CPC分类号： G06F11/348 , Y02D10/34
摘要： A system for monitoring a large number of simultaneous events implements a hybrid counter array device having a first counter portion comprising counter devices, each counter device for receiving signals representing occurrences of events from an event source and providing a first count value corresponding to a lower order bits of the hybrid counter array. A second counter portion comprises a memory array device having addressable memory locations in correspondence with the counter devices, each addressable memory location for storing a second count value representing higher order bits. A control device monitors each of the counter devices and initiates updating a value of a corresponding second count value stored at the corresponding addressable memory location. The system includes interrupt pre-indication for providing fast interrupt trigger to a processor device when a count value related to an event equals a threshold value.
摘要翻译：一种用于监视大量同时事件的系统实现具有包括计数器装置的第一计数器部分的混合计数器阵列装置，每个计数器装置用于接收表示从事件源发生的事件的信号，并提供对应于较低次序的第一计数值混合计数器阵列的位。第二计数器部分包括具有与计数器装置对应的可寻址存储器位置的存储器阵列器件，每个可寻址存储器位置用于存储表示较高位的第二计数值。控制装置监视每个计数器装置并且启动更新存储在相应的可寻址存储器位置处的对应的第二计数值的值。当与事件相关的计数值等于阈值时，该系统包括用于向处理器设备提供快速中断触发的中断预指示。

90. 发明授权

US07797503B2 Configurable memory system and method for providing atomic counting operations in a memory device 有权
标题翻译：可配置的存储器系统和方法，用于在存储器件中提供原子计数操作
公开(公告)号：US07797503B2
公开(公告)日：2010-09-14
申请号：US11768812
申请日：2007-06-26
申请人： Ralph E. Bellofatto , Alan G. Gara , Mark E. Giampapa , Martin Ohmacht
发明人： Ralph E. Bellofatto , Alan G. Gara , Mark E. Giampapa , Martin Ohmacht
IPC分类号： G06F12/00
CPC分类号： G06F12/10 , G06F9/3004 , G06F9/30185 , G06F9/3834 , G06F9/3851 , G06F9/3861 , G06F12/0292 , G06F12/1027 , G06F2212/1044 , G06F2212/206
摘要： A memory system and method for providing atomic memory-based counter operations to operating systems and applications that make most efficient use of counter-backing memory and virtual and physical address space, while simplifying operating system memory management, and enabling the counter-backing memory to be used for purposes other than counter-backing storage when desired. The encoding and address decoding enabled by the invention provides all this functionality through a combination of software and hardware.
摘要翻译：一种用于向操作系统和应用提供基于原子的存储器的计数器操作的存储器系统和方法，所述操作系统和应用可最有效地利用反向存储器和虚拟和物理地址空间，同时简化操作系统存储器管理，在需要的时候用于除背板存储之外的目的。通过本发明实现的编码和地址解码通过软件和硬件的组合来提供所有这些功能。

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