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81. 发明授权

US08750040B2 Memory devices having source lines directly coupled to body regions and methods 有权
标题翻译：具有直接耦合到身体区域的源极线的存储器件和方法
公开(公告)号：US08750040B2
公开(公告)日：2014-06-10
申请号：US13011223
申请日：2011-01-21
申请人： Akira Goda
发明人： Akira Goda
IPC分类号： G11C16/04
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/10 , H01L27/11524 , H01L27/11556
摘要： Memory devices, memory cell strings and methods of operating memory devices are shown. Configurations described include directly coupling an elongated body region to a source line. Configurations and methods shown should provide a reliable bias to a body region for memory operations such as erasing.
摘要翻译：显示了存储器件，存储器单元串和操作存储器件的方法。所描述的配置包括将细长体区直接耦合到源线。显示的配置和方法应为存储器操作（如擦除）提供可靠的身体区域偏置。

82. 发明授权

US08681562B2 Memories and methods of programming memories 有权
标题翻译：记忆和程序记忆的方法
公开(公告)号：US08681562B2
公开(公告)日：2014-03-25
申请号：US13051599
申请日：2011-03-18
申请人： Pranav Kalavade , Akira Goda , Tommaso Vali , Violante Moschiano
发明人： Pranav Kalavade , Akira Goda , Tommaso Vali , Violante Moschiano
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3454 , G11C16/3459
摘要： Apparatus and methods for adjusting programming for upper pages of memories are disclosed. In at least one embodiment, a threshold voltage distribution upper limit is determined after a single programming pulse for lower page programming, and upper page programming start voltages are adjusted based on the determined upper limit of the threshold voltage distribution.
摘要翻译：公开了用于调整存储器上部页面编程的装置和方法。在至少一个实施例中，在用于较低页编程的单个编程脉冲之后确定阈值电压分布上限，并且基于所确定的阈值电压分布的上限来调整上页编程开始电压。

83. 发明申请

US20140029345A1 MEMORY DEVICES AND PROGRAMMING MEMORY ARRAYS THEREOF 有权
标题翻译：存储器件和编程存储器阵列
公开(公告)号：US20140029345A1
公开(公告)日：2014-01-30
申请号：US13561637
申请日：2012-07-30
申请人： Akira Goda , Haitao Liu , Krishna Parat
发明人： Akira Goda , Haitao Liu , Krishna Parat
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C16/0483 , H01L27/11556 , H01L27/11582
摘要： An embodiment of a method includes decreasing a difference of a voltage applied to a first select gate minus a voltage applied to a source while the first select gate is off, decreasing a difference of a voltage applied to a second select gate minus a voltage applied to a data line while the second select gate is off, and increasing a voltage of a signal applied to a selected access line that is coupled to an untargeted memory cell in a string of memory cells coupled to the first and second select gates to a program voltage after or substantially concurrently with decreasing the difference of the voltage applied to the first select gate minus the voltage applied to the source and with decreasing the difference of the voltage applied to the second select gate minus the voltage applied to the data line.
摘要翻译：一种方法的实施例包括在第一选择栅极截止时减小施加到第一选择栅极的电压减去施加到源极的电压的差异，减小施加到第二选择栅极的电压的差减去施加到数据线，而第二选择栅极关闭，以及增加施加到所选择的存取线的信号的电压，该选择的存取线耦合到耦合到第一和第二选择栅极的一串存储单元中的非目标存储器单元到编程电压之后或基本同时地减小施加到第一选择栅极的电压的差减去施加到源极的电压，并且减小施加到第二选择栅极的电压的差减去施加到数据线的电压。

84. 发明授权

US08634252B2 Methods of operating a memory device having a buried boosting plate 有权
标题翻译：操作具有埋地升压板的存储器件的方法
公开(公告)号：US08634252B2
公开(公告)日：2014-01-21
申请号：US13351148
申请日：2012-01-16
申请人： Akira Goda
发明人： Akira Goda
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , H01L21/84 , H01L27/11526 , H01L27/11529 , H01L27/1203
摘要： Memory devices are disclosed, such as those that include a semiconductor-on-insulator (SOI) NAND memory array having a boosting plate. The boosting plate may be disposed in an insulator layer of the SOI substrate such that the boosting plate exerts a capacitive coupling effect on a p-well of the memory array. Such a boosting plate may be used to boost the p-well during program and erase operations of the memory array. During a read operation, the boosting plate may be grounded to minimize interaction with p-well. Systems including the memory array and methods of operating the memory array are also disclosed.
摘要翻译：公开了存储器件，例如包括具有升压板的绝缘体上半导体（SOI）NAND存储器阵列的存储器件。升压板可以设置在SOI衬底的绝缘体层中，使得升压板对存储器阵列的p阱施加电容耦合效应。这种升压板可用于在存储器阵列的编程和擦除操作期间升压p阱。在读取操作期间，升压板可以接地以最小化与p阱的相互作用。还公开了包括存储器阵列的系统和操作存储器阵列的方法。

85. 发明授权

US08514624B2 In-field block retiring 有权
标题翻译：现场块退役
公开(公告)号：US08514624B2
公开(公告)日：2013-08-20
申请号：US13165416
申请日：2011-06-21
申请人： Krishna K. Parat , Akira Goda , Koichi Kawai , Brian J. Soderling , Jeremy Binfet , Arnaud A. Furnemont , Tejas Krishnamohan , Tyson M. Stichka , Giuseppina Puzzilli
发明人： Krishna K. Parat , Akira Goda , Koichi Kawai , Brian J. Soderling , Jeremy Binfet , Arnaud A. Furnemont , Tejas Krishnamohan , Tyson M. Stichka , Giuseppina Puzzilli
IPC分类号： G11C16/04
CPC分类号： G11C29/765 , G11C11/5628 , G11C16/0483 , G11C16/16 , G11C16/349 , G11C29/789
摘要： Memory devices and methods are disclosed, including a method involving erasing a block of memory cells. After erasing the block, and before subsequent programming of the block, a number of bad strings in the block are determined based on charge accumulation on select gate transistors. The block is retired from use if the number of bad strings exceeds a threshold. Additional embodiments are disclosed.
摘要翻译：公开了存储器件和方法，包括涉及擦除存储器单元块的方法。在擦除块之后，并且在块的后续编程之前，基于选择栅晶体管上的电荷积累来确定块中的多个不良串。如果坏字符串的数量超过阈值，则该块将从使用中退出。公开了另外的实施例。

86. 发明申请

US20130088916A1 DISTURB VERIFY FOR PROGRAMMING MEMORY CELLS 有权
标题翻译：用于编程记忆细胞的干扰验证
公开(公告)号：US20130088916A1
公开(公告)日：2013-04-11
申请号：US13267602
申请日：2011-10-06
申请人： Karthik Sarpatwari , Akira Goda
发明人： Karthik Sarpatwari , Akira Goda
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3418 , G11C16/3454
摘要： Apparatuses and methods for disturb verify for programming operations are described. Programming memory cells can include applying a number of programming pulses to a first memory cell, performing a disturb verify operation on a second memory cell adjacent to the first memory cell, and inhibiting the first memory cell from further programming in response to the second memory cell failing the disturb verify operation. Other apparatuses and methods are also disclosed.
摘要翻译：描述用于编程操作的干扰校验的装置和方法。编程存储器单元可以包括将多个编程脉冲施加到第一存储器单元，对与第一存储器单元相邻的第二存储单元执行干扰校验操作，以及响应于第二存储器单元禁止第一存储器单元进一步编程无法进行干扰验证操作。还公开了其它装置和方法。

87. 发明申请

US20130049093A1 METHODS AND APPARATUSES INCLUDING MEMORY CELLS WITH AIR GAPS AND OTHER LOW DIELECTRIC CONSTANT MATERIALS 有权
标题翻译：包括具有空气GAPS和其他低介电常数材料的记忆细胞的方法和装置
公开(公告)号：US20130049093A1
公开(公告)日：2013-02-28
申请号：US13222367
申请日：2011-08-31
申请人： Minsoo Lee , Akira Goda
发明人： Minsoo Lee , Akira Goda
IPC分类号： H01L29/788 , H01L21/28
CPC分类号： H01L21/28273 , H01L21/28282 , H01L21/764 , H01L27/11519 , H01L27/11556 , H01L27/11565 , H01L27/11582 , H01L29/42324 , H01L29/4234 , H01L29/66825 , H01L29/7889
摘要： Various embodiments include apparatuses and methods of forming the same. One such apparatus can include a first dielectric material and a second dielectric material, and a conductive material between the first dielectric material and the second dielectric material. A charge storage element, such as a floating gate or charge trap, is between the first dielectric material and the second dielectric material and adjacent to the conductive material. The charge storage element has a first surface and a second surface. The first and second surfaces are substantially separated from the first dielectric material and the second dielectric material, respectively, by a first air gap and a second air gap. Additional apparatuses and methods are disclosed.
摘要翻译：各种实施例包括其形成装置和方法。一种这样的设备可以包括第一介电材料和第二介电材料，以及在第一介电材料和第二介电材料之间的导电材料。诸如浮动栅极或电荷阱的电荷存储元件位于第一介电材料和第二电介质材料之间并且与导电材料相邻。电荷存储元件具有第一表面和第二表面。第一和第二表面分别通过第一气隙和第二气隙与第一介电材料和第二电介质材料分开。公开了附加的装置和方法。

88. 发明申请

US20130016569A1 MEMORY DEVICE HAVING IMPROVED PROGRAMMING OPERATION 有权
标题翻译：具有改进的编程操作的存储器件
公开(公告)号：US20130016569A1
公开(公告)日：2013-01-17
申请号：US13621052
申请日：2012-09-15
申请人： Prashant S. Damle , Krishna Parat , Alessandro Torsi , Carlo Musilli , Kalpana Vakati , Akira Goda
发明人： Prashant S. Damle , Krishna Parat , Alessandro Torsi , Carlo Musilli , Kalpana Vakati , Akira Goda
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C16/3404 , G11C16/0483 , G11C16/10 , G11C16/32
摘要： Some embodiments include methods and devices having a module and memory cells. The module is configured to reduce the amount of electrons in the sources and drains of the memory cells during a programming operation.
摘要翻译：一些实施例包括具有模块和存储器单元的方法和装置。该模块被配置为在编程操作期间减少存储器单元的源极和漏极中的电子量。

89. 发明授权

US08264885B2 Method for memory cell erasure with a programming monitor of reference cells 有权
标题翻译：用参考单元的编程监视器进行存储单元擦除的方法
公开(公告)号：US08264885B2
公开(公告)日：2012-09-11
申请号：US13082965
申请日：2011-04-08
申请人： Akira Goda , Andrei Mihnea
发明人： Akira Goda , Andrei Mihnea
IPC分类号： G11C16/16
CPC分类号： G11C16/06 , G11C11/5628 , G11C11/5635 , G11C16/0483 , G11C16/10 , G11C2211/5621 , G11C2211/5634
摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for operating memory cells. One method includes: performing an erase operation on a selected group of memory cells, the selected group including a number of reference cells and a number of data cells; performing a programming monitor operation on the number of reference cells as part of the erase operation; and determining a number of particular operating parameters associated with operating the number of data cells at least partially based on the programming monitor operation performed on the number of reference cells.
摘要翻译：本公开的实施例提供用于操作存储器单元的方法，设备，模块和系统。一种方法包括：对所选择的一组存储器单元执行擦除操作，所选择的组包括多个参考单元和多个数据单元; 对作为擦除操作的一部分的参考单元的数量进行编程监视操作; 以及至少部分地基于对参考单元的数量执行的编程监视操作来确定与操作所述数据单元的数量相关联的特定操作参数的数量。

90. 发明授权

US08208278B2 Couplings within memory devices 有权
标题翻译：存储器件内的联轴器
公开(公告)号：US08208278B2
公开(公告)日：2012-06-26
申请号：US12637163
申请日：2009-12-14
申请人： Akira Goda , Seiichi Aritome
发明人： Akira Goda , Seiichi Aritome
IPC分类号： G11C5/06
CPC分类号： G11C7/02 , G11C7/1036 , H01L27/105 , H01L27/11517 , H01L27/11526
摘要： A memory device includes a first bit line coupled to a first source/drain region of a first multiplexer gate, a second bit line coupled to a first source/drain region of a second multiplexer gate, and a sensing device having an input coupled to a second source/drain region of the first multiplexer gate and a second source/drain region of the second multiplexer gate. The input of the sensing device is formed at a vertical level that is different than a vertical level at which at least one of the first and second bit lines is formed.
摘要翻译：存储器件包括耦合到第一多路复用器门的第一源极/漏极区域的第一位线，耦合到第二多路复用器栅极的第一源极/漏极区域的第二位线以及耦合到第二多路复用器栅极的输入的感测器件第一多路复用器栅极的第二源极/漏极区域和第二多路复用器栅极的第二源极/漏极区域。感测装置的输入形成在与形成第一和第二位线中的至少一个的垂直电平不同的垂直电平处。

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