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    • 82. 发明授权
    • Semiconductor device
    • 半导体器件
    • US09105716B2
    • 2015-08-11
    • US12944632
    • 2010-11-11
    • Miwako AkiyamaYusuke KawaguchiYoshihiro Yamaguchi
    • Miwako AkiyamaYusuke KawaguchiYoshihiro Yamaguchi
    • H01L21/336H01L29/78H01L29/06H01L29/10H01L29/66H01L21/265H01L29/08H01L29/417
    • H01L29/7813H01L21/26586H01L29/0634H01L29/0869H01L29/0878H01L29/1095H01L29/41741H01L29/41766H01L29/66727H01L29/66734
    • A semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type provided on a main surface of the first semiconductor layer and having a lower impurity concentration than that of the first semiconductor layer; a third semiconductor layer of a second conductivity type provided on the second semiconductor layer; a fourth semiconductor layer of the first conductivity type selectively provided on the third semiconductor layer; a gate electrode provided in a trench passing through the third semiconductor layer and reaching the second semiconductor layer; a first main electrode contacting the fourth semiconductor layer and contacting the third semiconductor layer through a contact groove provided to pass through the fourth semiconductor layer between the contiguous gate electrodes; a second main electrode provided on an opposite surface to the main surface of the first semiconductor layer; and a fifth semiconductor layer of the second conductivity type provided in an interior portion of the second semiconductor layer corresponding to a part under the contact groove. An uppermost portion of the fifth semiconductor layer contacts the third semiconductor layer, a lowermost portion of the fifth semiconductor layer has a higher impurity concentration than that of the other portion in the fifth semiconductor layer and is located in the second semiconductor layer and not contacting the first semiconductor layer, and the fifth semiconductor layer is narrower from the uppermost portion to the lower most portion.
    • 半导体器件包括:第一导电类型的第一半导体层; 第一导电类型的第二半导体层设置在第一半导体层的主表面上并且具有比第一半导体层的杂质浓度低的第二半导体层; 设置在第二半导体层上的第二导电类型的第三半导体层; 选择性地设置在第三半导体层上的第一导电类型的第四半导体层; 设置在穿过所述第三半导体层并到达所述第二半导体层的沟槽中的栅电极; 与所述第四半导体层接触的第一主电极,并且通过设置成在所述连续的栅电极之间穿过所述第四半导体层的接触槽使所述第三半导体层接触; 设置在与所述第一半导体层的主表面相反的表面上的第二主电极; 以及第二导电类型的第五半导体层,设置在与所述接触槽下方的部分对应的所述第二半导体层的内部。 第五半导体层的最上部与第三半导体层接触,第五半导体层的最下部分的杂质浓度比第五半导体层中的其他部分杂质浓度高,位于第二半导体层中, 第一半导体层,第五半导体层从最上部到最下部较窄。
    • 84. 发明授权
    • Semiconductor device
    • 半导体器件
    • US08008715B2
    • 2011-08-30
    • US12185630
    • 2008-08-04
    • Yusuke KawaguchiKazuya NakayamaTsuyoshi OhtaTakeshi UchiharaTakahiro KawanoYuji Kato
    • Yusuke KawaguchiKazuya NakayamaTsuyoshi OhtaTakeshi UchiharaTakahiro KawanoYuji Kato
    • H01L29/78
    • H01L29/7813H01L29/42372H01L29/42376H01L29/4238H01L29/7811
    • There is provided a semiconductor device comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided on the first semiconductor layer of the first conductivity type; a semiconductor region of the first conductivity type selectively provided on a front surface portion of the second semiconductor layer of the second conductivity type; a first main electrode provided in contact with a surface of the semiconductor region; a second main electrode provided on a side of the first semiconductor layer of the first conductivity type, the side being opposite to the surface on which the second semiconductor layer of the second conductivity type is provided; a gate wiring provided on the second semiconductor layer of the second conductivity type around an element region in which the semiconductor region is provided; a trench penetrating the second semiconductor layer of the second conductivity type to reach the first semiconductor layer of the first conductivity type, and also extending under the element region and the gate wiring; a gate electrode provided inside the trench in the element region with a gate insulating film interposed in between; and a gate electrode lead portion provided inside the trench under the gate wiring with the gate insulating film interposed in between, and contacting the gate wiring and the gate electrode.
    • 提供一种半导体器件,包括:第一导电类型的第一半导体层; 设置在第一导电类型的第一半导体层上的第二导电类型的第二半导体层; 选择性地设置在第二导电类型的第二半导体层的前表面部分上的第一导电类型的半导体区域; 设置成与半导体区域的表面接触的第一主电极; 设置在第一导电类型的第一半导体层的一侧的第二主电极,与设置有第二导电类型的第二半导体层的表面相对的一侧; 围绕设置有半导体区域的元件区域设置在第二导电类型的第二半导体层上的栅极布线; 穿过第二导电类型的第二半导体层的沟槽到达第一导电类型的第一半导体层,并且还在元件区域和栅极布线之下延伸; 设置在所述元件区域的所述沟槽内部的栅电极,其间插入有栅极绝缘膜; 以及栅极引线部分,其设置在栅极布线下方的沟槽内部,栅极绝缘膜介于其间并与栅极布线和栅电极接触。
    • 90. 发明申请
    • SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
    • 半导体器件及其制造方法
    • US20080283909A1
    • 2008-11-20
    • US12122165
    • 2008-05-16
    • Miwako AkiyamaYusuke KawaguchiYoshihiro Yamaguchi
    • Miwako AkiyamaYusuke KawaguchiYoshihiro Yamaguchi
    • H01L29/78H01L21/336
    • H01L29/7813H01L21/26586H01L29/1095H01L29/41766H01L29/66727H01L29/66734
    • A semiconductor device includes a second-conductivity-type base region provided on a first-conductivity-type semiconductor layer, a first-conductivity-type source region provided on the second-conductivity-type base region, a gate insulating film covering an inner wall of a trench which passes through the second-conductivity-type base region and reaching the first-conductivity-type semiconductor layer, a gate electrode buried in the trench via the gate insulating film, and a second-conductivity-type region being adjacent to the second-conductivity-type base region below the first-conductivity-type source region, spaced from the gate insulating film, and having a higher impurity concentration than the second-conductivity-type base region. c≧d is satisfied, where d is a depth from an upper surface of the first-conductivity-type source region to a lower end of the gate electrode, and c is a depth from an upper surface of the first-conductivity-type source region to a lower surface of the second-conductivity-type base region.
    • 半导体器件包括设置在第一导电型半导体层上的第二导电型基极区域,设置在第二导电型基极区域上的第一导电型源极区域,覆盖内壁的栅极绝缘膜 通过所述第二导电型基极区域并到达所述第一导电型半导体层的沟槽,经由所述栅极绝缘膜埋设在所述沟槽中的栅电极,以及与所述第二导电型基极区相邻的第二导电型区域 与第一导电型源极区域相邻的第二导电型基极区域,与栅极绝缘膜间隔开,并且具有比第二导电型基极区域更高的杂质浓度。 c> = d,其中d是从第一导电型源极区域的上表面到栅极电极的下端的深度,c是从第一导电型源极区域的上表面开始的深度 源极区域延伸到第二导电型基极区域的下表面。