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81. 发明授权

US06335282B1 Method of forming a titanium comprising layer and method of forming a conductive silicide contact 失效
标题翻译：形成钛的层的方法和形成导电硅化物接触的方法
公开(公告)号：US06335282B1
公开(公告)日：2002-01-01
申请号：US09383888
申请日：1999-08-26
申请人： Sujit Sharan , Gurtej S. Sandhu
发明人： Sujit Sharan , Gurtej S. Sandhu
IPC分类号： H01L2144
CPC分类号： H01L21/28568 , H01L21/28518
摘要： The invention includes methods of forming titanium comprising layers, and methods of forming conductive silicide contacts. In one implementation, a method of forming a titanium comprising layer includes chemical vapor depositing a layer a majority of which comprises elemental titanium, titanium silicide or a mixture thereof over a substrate using a precursor gas chemistry comprising titanium and chlorine. The layer comprises chlorine from the precursor gas chemistry. The layer is exposed to a hydrogen containing plasma effective to drive chlorine from the layer. In one implementation, a method of forming a conductive silicide contact includes forming an insulating material over a silicon comprising substrate. An opening is formed into the insulating material over a node location on the silicon comprising substrate to which electrical connection is desired. A layer is chemical vapor deposited over the substrate using a precursor gas chemistry comprising titanium and chlorine. The layer comprises chlorine from the precursor gas chemistry. The depositing forms a majority of the layer over the node location as titanium silicide, and a majority of the layer over the insulating material as elemental titanium. At least the majority titanium silicide portion of the layer is exposed to a hydrogen containing plasma effective to drive chlorine therefrom.
摘要翻译：本发明包括形成包含层的钛的方法以及形成导电硅化物接触的方法。在一个实施方案中，形成包含钛的层的方法包括化学气相沉积层，其中大部分包括元素钛，硅化钛或其混合物，使用包含钛和氯的前体气体化学物质在衬底上。该层包括来自前体气体化学物质的氯。该层暴露于含氢等离子体中，有效地驱使层中的氯。在一个实施方案中，形成导电硅化物接触的方法包括在包含硅的衬底上形成绝缘材料。在需要电连接的硅包含衬底上的节点位置上形成绝缘材料的开口。使用包含钛和氯的前体气体化学，在衬底上化学气相沉积一层。该层包括来自前体气体化学物质的氯。沉积形成作为硅化钛的节点位置上的层的大部分，绝缘材料上的绝大多数层作为元素钛。至少该层的多数硅化钛部分暴露于含氢等离子体中，从而驱动氯。

82. 发明授权

US06258724B1 Low dielectric constant dielectric films and process for making the same 有权
标题翻译：低介电常数介电膜及其制造方法
公开(公告)号：US06258724B1
公开(公告)日：2001-07-10
申请号：US09541160
申请日：2000-03-31
申请人： Sujit Sharan
发明人： Sujit Sharan
IPC分类号： H01L21302
CPC分类号： H01L21/76801 , H01L21/3105 , H01L21/31612 , H01L21/7682 , H01L2221/1047 , Y10S977/712 , Y10S977/78 , Y10S977/831 , Y10S977/891
摘要： A low dielectric constant material and a process for controllably reducing the dielectric constant of a layer of such material is provided and comprises the step of exposing the layer of dielectric material to a concentration of an oxygen plasma at a temperature and a pressure sufficient for the oxygen plasma to etch the layer of dielectric material to form voids in the layer of dielectric material. The process may also include the step of controlling the reduction of the dielectric constant by controlling the size and density of the voids. The size and density of the voids can be controlled by varying the pressure under which the reaction takes place, by varying the temperature at which the reaction takes place, by varying the concentration of the oxygen plasma used in the reaction or by varying a combination of these parameters. The process of the present invention is particularly useful in the fabrication of semiconductor devices.
摘要翻译：提供了低介电常数材料和用于可控地降低这种材料层的介电常数的方法，并且包括以下步骤：在足以使氧气的温度和压力下将电介质材料层暴露于氧等离子体的浓度等离子体以蚀刻介电材料层以在介电材料层中形成空隙。该方法还可以包括通过控制空隙的尺寸和密度来控制介电常数的降低的步骤。空隙的大小和密度可以通过改变反应发生的压力，通过改变反应的温度，通过改变反应中使用的氧等离子体的浓度或通过改变反应的组合来控制这些参数。本发明的方法在半导体器件的制造中特别有用。

83. 发明授权

US06239029B1 Sacrificial germanium layer for formation of a contact 有权
标题翻译：用于形成接触的牺牲锗层
公开(公告)号：US06239029B1
公开(公告)日：2001-05-29
申请号：US09146850
申请日：1998-09-03
申请人： Jeffrey Honeycutt , Sujit Sharan
发明人： Jeffrey Honeycutt , Sujit Sharan
IPC分类号： H01L2144
CPC分类号： H01L21/76858 , H01L21/28518 , H01L21/76843 , H01L21/76846 , H01L21/76855 , H01L21/76856 , H01L23/485 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： A contact to a semiconductor substrate including a contact opening extending through an insulating layer to a doped active region of the semiconductor substrate. The contact opening can have a relatively high aspect ratio of 2:1 or greater. The contact further includes a refractory metal germanosilicide region at the bottom of the contact opening, a refractory metal germanide layer at the sidewalls of the contact opening, and an overlying refractory metal nitride layer. The refractory metals of the invention include at least tantalum, titanium, cobalt and mixtures thereof. The contact is metallized, preferably using tungsten or aluminum. The method of manufacturing the contact comprises etching the contact opening. A germane gas is used to clean native silicon dioxide from the bottom of the contact opening and to deposit a germanium layer thereon. A refractory metal layer is deposited over the germanium layer. After annealing in a nitrogen atmosphere at a temperature of about 600° C. or less, the contact opening is metallized with tungsten or aluminum.
摘要翻译：与半导体衬底的接触，包括延伸穿过绝缘层到半导体衬底的掺杂有源区的接触开口。接触开口可以具有2:1或更大的相对高的纵横比。触点还包括位于接触开口底部的难熔金属锗硅化物区域，位于接触开口侧壁处的难熔金属锗化物层和上覆难熔金属氮化物层。本发明的难熔金属至少包括钽，钛，钴及其混合物。接触金属化，优选使用钨或铝。制造接触的方法包括蚀刻接触开口。锗烷气体用于从接触开口的底部清洗天然二氧化硅并在其上沉积锗层。难熔金属层沉积在锗层上。在氮气气氛中在约600℃或更低的温度下退火后，接触开口用钨或铝金属化。

84. 发明授权

US06235646B1 RF powered plasma enhanced chemical vapor deposition reactor and methods of effecting plasma enhanced chemical vapor deposition 有权
标题翻译： RF功率等离子体增强化学气相沉积反应器和实现等离子体增强化学气相沉积的方法
公开(公告)号：US06235646B1
公开(公告)日：2001-05-22
申请号：US09670982
申请日：2000-09-26
申请人： Sujit Sharan , Gurtej S. Sandhu , Paul Smith , Mei Chang
发明人： Sujit Sharan , Gurtej S. Sandhu , Paul Smith , Mei Chang
IPC分类号： H01L2131
CPC分类号： H01J37/32174 , C23C16/505 , H01J37/32082 , H01J37/321 , Y10S438/961
摘要： Plasma enhanced chemical vapor deposition (PECVD) reactors and methods of effecting the same are described. In accordance with a preferred implementation, a reaction chamber includes first and second electrodes operably associated therewith. A single RF power generator is connected to an RF power splitter which splits the RF power and applies the split power to both the first and second electrodes. Preferably, power which is applied to both electrodes is in accordance with a power ratio as between electrodes which is other than a 1:1 ratio. In accordance with one preferred aspect, the reaction chamber comprises part of a parallel plate PECVD system. In accordance with another preferred aspect, the reaction chamber comprises part of an inductive coil PECVD system. The power ratio is preferably adjustable and can be varied. One manner of effecting a power ratio adjustment is to vary respective electrode surface areas. Another manner of effecting the adjustment is to provide a power splitter which enables the output power thereof to be varied. PECVD processing methods are described as well.
摘要翻译：描述了等离子体增强化学气相沉积（PECVD）反应器及其实现方法。根据优选的实施方案，反应室包括与其可操作地相关联的第一和第二电极。单个RF功率发生器连接到RF功率分配器，RF功率分配器分离RF功率并将分裂功率施加到第一和第二电极两者。优选地，施加到两个电极的功率与不同于1:1的电极之间的功率比一致。根据一个优选方面，反应室包括平行板PECVD系统的一部分。根据另一个优选的方面，反应室包括感应线圈PECVD系统的一部分。功率比优选是可调节的并且可以变化。实现功率比调整的一种方式是改变各个电极表面积。实现调整的另一种方式是提供能够改变输出功率的功率分配器。还描述了PECVD处理方法。

85. 发明授权

US06227141B1 RF powered plasma enhanced chemical vapor deposition reactor and methods 有权
标题翻译：射频等离子体增强化学气相沉积反应器和方法
公开(公告)号：US06227141B1
公开(公告)日：2001-05-08
申请号：US09597659
申请日：2000-06-19
申请人： Sujit Sharan , Gurtej S. Sandhu , Paul Smith
发明人： Sujit Sharan , Gurtej S. Sandhu , Paul Smith
IPC分类号： C23C1600
CPC分类号： H01J37/32174 , H01J37/32165
摘要： Plasma enhanced chemical vapor deposition (PECVD) reactors and methods of effecting the same are described. In a preferred implementation, a PECVD reactor includes a processing chamber having a first electrode therewithin. A second electrode is disposed within the chamber and is configured for supporting at least one semiconductor workpiece for processing. A first RF power source delivers RF power of a first frequency to the first electrode. A second RF power source delivers RF power of a second frequency to the second electrode. Preferably the first and second frequencies are different from one another, and even more preferably, the first frequency is greater than the second frequency. The preferred reactor includes a thermocouple which provides temperature information relative to one of the electrodes. According to a preferred implementation, the power loop developed by the first RF power source is grounded interiorly of the chamber in a manner which reduces if not eliminates interference with other reactor components including the thermocouple.
摘要翻译：描述了等离子体增强化学气相沉积（PECVD）反应器及其实现方法。在优选的实施方案中，PECVD反应器包括其中具有第一电极的处理室。第二电极设置在室内并且被配置为支撑至少一个半导体工件用于处理。第一RF电源将第一频率的RF功率提供给第一电极。第二RF电源将第二频率的RF功率提供给第二电极。优选地，第一和第二频率彼此不同，并且甚至更优选地，第一频率大于第二频率。优选的反应器包括提供相对于一个电极的温度信息的热电偶。根据优选实施方案，由第一RF电源开发的功率回路以室内接地，其方式如果不消除对包括热电偶的其它反应器部件的干扰，则减小。

86. 发明授权

US6140249A Low dielectric constant dielectric films and process for making the same 有权
标题翻译：低介电常数介电膜及其制造方法
公开(公告)号：US6140249A
公开(公告)日：2000-10-31
申请号：US384668
申请日：1999-08-27
申请人： Sujit Sharan
发明人： Sujit Sharan
IPC分类号： H01L21/3105 , H01L21/316 , H01L21/768 , H01L21/31
CPC分类号： H01L21/76801 , H01L21/3105 , H01L21/7682 , H01L21/31612 , H01L2221/1047 , Y10S977/712 , Y10S977/78 , Y10S977/831 , Y10S977/891
摘要： A low dielectric constant material and a process for controllably reducing the dielectric constant of a layer of such material is provided and comprises the step of exposing the layer of dielectric material to a concentration of an oxygen plasma at a temperature and a pressure sufficient for the oxygen plasma to etch the layer of dielectric material to form voids in the layer of dielectric material. The process may also include the step of controlling the reduction of the dielectric constant by controlling the size and density of the voids. The size and density of the voids can be controlled by varying the pressure under which the reaction takes place, by varying the temperature at which the reaction takes place, by varying the concentration of the oxygen plasma used in the reaction or by varying a combination of these parameters. The process of the present invention is particularly useful in the fabrication of semiconductor devices.
摘要翻译：提供了低介电常数材料和用于可控地降低这种材料层的介电常数的方法，并且包括以下步骤：在足以使氧气的温度和压力下将电介质材料层暴露于氧等离子体的浓度等离子体以蚀刻介电材料层以在介电材料层中形成空隙。该方法还可以包括通过控制空隙的尺寸和密度来控制介电常数的降低的步骤。空隙的大小和密度可以通过改变反应发生的压力，通过改变反应的温度，通过改变反应中使用的氧等离子体的浓度或通过改变反应的组合来控制这些参数。本发明的方法在半导体器件的制造中特别有用。

87. 发明授权

US6077754A Methods of forming a silicon nitride film, a capacitor dielectric layer and a capacitor 失效
标题翻译：形成氮化硅膜，电容器电介质层和电容器的方法
公开(公告)号：US6077754A
公开(公告)日：2000-06-20
申请号：US18925
申请日：1998-02-05
申请人： Anand Srinivasan , Sujit Sharan , Gurtej S. Sandhu
发明人： Anand Srinivasan , Sujit Sharan , Gurtej S. Sandhu
IPC分类号： H01L21/02 , H01L21/318
CPC分类号： H01L28/40 , H01L21/3185
摘要： A method of forming silicon nitride includes, a) forming a first layer comprising silicon nitride over a substrate; b) forming a second layer comprising silicon on the first layer; and c) nitridizing silicon of the second layer into silicon nitride to form a silicon nitride comprising layer, said silicon nitride comprising layer comprising silicon nitride of the first and second layers. Further, a method of forming a capacitor dielectric layer of silicon nitride includes, a) forming a first capacitor plate layer; b) forming a first silicon nitride layer over the first capacitor plate layer; c) forming a silicon layer on the silicon nitride layer; d) nitridizing the silicon layer into a second silicon nitride layer; and e) forming a second capacitor plate layer over the second silicon nitride layer. Also, a method of forming a capacitor dielectric layer over a capacitor plate layer includes, a) forming a first layer of dielectric material over a capacitor plate layer; b) conducting a pin-hole widening wet etch of the first layer; and c) after the wet etch, forming a pin-hole plugging second layer of dielectric material on the first layer and within the widened pin-holes.
摘要翻译：一种形成氮化硅的方法包括：a）在衬底上形成包含氮化硅的第一层; b）在第一层上形成包含硅的第二层; 以及c）将所述第二层的硅氮化成氮化硅以形成包含氮化硅的层，所述氮化硅层包括第一层和第二层的氮化硅。此外，形成氮化硅电容器电介质层的方法包括：a）形成第一电容器板层; b）在所述第一电容器板层上形成第一氮化硅层; c）在氮化硅层上形成硅层; d）将硅层氮化成第二氮化硅层; 以及e）在所述第二氮化硅层上方形成第二电容器板层。此外，在电容器板层上形成电容器电介质层的方法包括：a）在电容器板层上形成介电材料的第一层; b）进行第一层的针孔加宽湿蚀刻; 以及c）在湿蚀刻之后，在第一层上和扩宽的针孔内形成针孔堵塞的第二介电材料层。

88. 发明申请

US20130341076A1 Package substrate and die spacer layers having a ceramic backbone 审中-公开
公开(公告)号：US20130341076A1
公开(公告)日：2013-12-26
申请号：US13987701
申请日：2013-08-22
申请人： Aleksandar Aleksov , Vladimir Noveski , Sujit Sharan , Shankar Ganapathysubramanian
发明人： Aleksandar Aleksov , Vladimir Noveski , Sujit Sharan , Shankar Ganapathysubramanian
IPC分类号： H05K1/02
CPC分类号： H05K1/0201 , H01L21/4807 , H01L23/15 , H01L23/49822 , H01L23/49827 , H01L2924/0002 , H01L2924/09701 , H05K1/0306 , H05K3/06 , H05K3/107 , H05K3/205 , H05K3/388 , H05K3/4617 , H05K3/4629 , H05K3/4647 , H05K2201/0175 , H05K2201/0187 , H05K2201/0376 , H05K2201/096 , H05K2201/09881 , H05K2203/0733 , Y10T29/49126 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165 , H01L2924/00
摘要： A layer or layers for use in package substrates and die spacers are described. The layer or layers include a plurality of ceramic wells lying within a plane and separated by metallic vias. Recesses within the ceramic wells are occupied by a dielectric filler material.

89. 发明申请

US20110122592A1 First-level interconnects with slender columns, and processes of forming same 审中-公开
标题翻译：具有细长柱的一级互连及其形成工艺
公开(公告)号：US20110122592A1
公开(公告)日：2011-05-26
申请号：US12592395
申请日：2009-11-24
申请人： Sanka Ganesan , Richard J. Harries , Sujit Sharan
发明人： Sanka Ganesan , Richard J. Harries , Sujit Sharan
IPC分类号： H05K7/02 , H01L21/60 , H01L23/488 , H01L23/48
CPC分类号： H01L24/14 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/0401 , H01L2224/05567 , H01L2224/05568 , H01L2224/10145 , H01L2224/13007 , H01L2224/13022 , H01L2224/13023 , H01L2224/13028 , H01L2224/13076 , H01L2224/13082 , H01L2224/13111 , H01L2224/13147 , H01L2224/1411 , H01L2224/1601 , H01L2224/1613 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/81191 , H01L2224/81192 , H01L2224/81193 , H01L2224/81411 , H01L2224/81815 , H01L2924/00013 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2924/351 , H01L2924/00014 , H01L2924/01049 , H01L2924/01083 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2224/05552 , H01L2924/00
摘要： A column is coupled to a last metallization of a die and the column is mated to a mounting substrate with that aid of a solder. The column may have the solder attached thereto before mating to the mounting substrate and the mounting substrate may be a bare-board (no solder mask) during the mating process. The column has an aspect ratio between 0.75 and 10.
摘要翻译：将柱与模具的最后金属化相结合，并且通过焊料的帮助将该柱配合到安装基板。在配合到安装基板之前，柱可以具有附着于其上的焊料，并且在配合过程期间，安装基板可以是裸板（无焊接掩模）。色谱柱的长宽比在0.75和10之间。

90. 发明申请

US20100327424A1 Multi-chip package and method of providing die-to-die interconnects in same 有权
标题翻译：多芯片封装和提供芯片间裸片互连的方法
公开(公告)号：US20100327424A1
公开(公告)日：2010-12-30
申请号：US12459007
申请日：2009-06-24
申请人： Henning Braunisch , Chia-Pin Chiu , Aleksandar Aleksov , Hinmeng Au , Stefanie M. Lotz , Johanna M. Swan , Sujit Sharan
发明人： Henning Braunisch , Chia-Pin Chiu , Aleksandar Aleksov , Hinmeng Au , Stefanie M. Lotz , Johanna M. Swan , Sujit Sharan
IPC分类号： H01L23/538 , H01L21/60
CPC分类号： H01L23/5385 , H01L21/6835 , H01L23/13 , H01L24/14 , H01L24/17 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/81 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L2224/0401 , H01L2224/13099 , H01L2224/1403 , H01L2224/141 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2224/32245 , H01L2224/45099 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/73207 , H01L2224/73253 , H01L2224/81001 , H01L2224/81005 , H01L2224/81801 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06562 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01076 , H01L2924/01079 , H01L2924/014 , H01L2924/10253 , H01L2924/10271 , H01L2924/10329 , H01L2924/12042 , H01L2924/1461 , H01L2924/15153 , H01L2924/19107 , H01L2924/351 , H01L2924/00
摘要： A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).
摘要翻译：多芯片封装包括具有第一侧面（111），相对的第二侧面（112）和从第一侧向第二侧延伸的第三侧面（213）的基板（110），第一模具（120））和附接到所述基板的第一侧的第二模具（130），以及邻近所述基板的第三侧并连接到所述第一模具和所述第二模具的桥接件（140）。基板的任何部分都不在桥下。该桥在第一管芯和第二管芯之间形成连接。或者，桥可以设置在衬底中的空腔（615,915）中，或者设置在衬底和裸片层（750）之间。该桥可以构成一个有源管芯，并且可以使用引线键连接到衬底（241,841,1141,1541）。

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