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热词
    • 90. 发明授权
    • Processing unit for a computer and a computer system incorporating such a processing unit
    • 用于计算机的处理单元和包含这种处理单元的计算机系统
    • US06216236B1
    • 2001-04-10
    • US09188903
    • 1998-11-10
    • Takeshi MiyaoManabu AraokaTomoaki NakamuraMasayuki TanjiShigenori KanekoKoji MasuiSaburou IijimaNobuyasu KanekawaShinichiro KanekawaYoshiki KobayashiHiroaki FukumaruKatsunori Tagiri
    • Takeshi MiyaoManabu AraokaTomoaki NakamuraMasayuki TanjiShigenori KanekoKoji MasuiSaburou IijimaNobuyasu KanekawaShinichiro KanekawaYoshiki KobayashiHiroaki FukumaruKatsunori Tagiri
    • G06F1134
    • G06F11/187G06F11/1064G06F11/141G06F11/1604G06F11/1641G06F11/1666G06F11/1679G06F11/18G06F11/181G06F11/184G06F11/185G06F11/20G06F11/2007G06F11/2028G06F11/203G06F11/2035G06F11/2043G06F12/0833G11C29/74
    • A computer system has a plurality of processing units (2-1,2-2,2-n) connected via one or more system buses (1-1,1-2). Each processing unit (2-1,2-2,2-n) has three or more processors (20-1,20-2,20-3) on a common support board (PL) and controlled by a common clock unit (1000). The three processors (20-1,20-2,20-3) perform the same operation and a fault in a processor (20-1,20-2, 20-3) is detected by comparison of the operations of the three processors (20-1,20-2,20-3). If one processor (20-1,20-2,20-3) fails, the operation can continue in the other two processors (20-1,20-2,20-3) of the processing unit (2-1,2-2,2-n), at least temporarily, before replacement of the entire processing unit (2-1,2-2, 2-n). Furthermore, the processing unit (2-1,2-2,2-n) may have a plurality of clocks (A,B) within the clock unit (1000), with a switching arrangement so that the processors (20-1,20-2,20-n) normally receive clock pulses from a main clock (A), but receive pulses from an auxiliary clock (B) if the main clock (A) fails. Switching between the main and auxiliary clock (A,B) involves comparison of the pulse duration from the clocks (A,B). Additionally, a plurality of cache memories (220,221) may be connected in common to the processors (20-1,20-2,20-3), so that failure of one cache memory (220,221) permits the processing unit (2-1,2-2,2-n) to continue to operate using the other cache memory (220,221). Coherence of the contents of the cache memories (220,221) may be achieved by direct comparison, and a comparison method can also be used to invalidate data in an internal cache memory (2020-1,2020-2,2020-3) of a processor (20-1,20-2,20-3) which differs from that in the external cache memory (220,221). Coherence of protocols may also ensure that data in caches (220,221) of the different processor units (2-1,2-2,2-n) are always correct.
    • 计算机系统具有经由一个或多个系统总线(1-1,1-2)连接的多个处理单元(2-1,2-2,2-n)。 每个处理单元(2-1,2-2,2-n)在公共支撑板(PL)上具有三个或更多个处理器(20-1,20-2,20-3),并由公共时钟单元 1000)。 三个处理器(20-1,20-2,20-3)执行相同的操作,并且通过比较三个处理器(20-1,20-2,20-3)的操作来检测处理器(20-1,20-2,20-3)中的故障 (20-1,20-2,20-3)。 如果一个处理器(20-1,20-2,20-3)失败,则可以在处理单元的其他两个处理器(20-1,20-2,20-3)中继续操作(2-1,2 -2,2-n),至少暂时在更换整个处理单元(2-1,2-2,2-n)之前。 此外,处理单元(2-1,2-2,2-n)可以在时钟单元(1000)内具有多个时钟(A,B),具有切换装置,使得处理器(20-1, 20-2,20-n)通常从主时钟(A)接收时钟脉冲,但是如果主时钟(A)发生故障,则从辅助时钟(B)接收脉冲。 在主时钟和辅助时钟(A,B)之间切换涉及从时钟(A,B)的脉冲持续时间的比较。 另外,多个高速缓冲存储器(220,221)可以共同地连接到处理器(20-1,20-2,20-3),使得一个高速缓冲存储器(220,221)的故障允许处理单元(2-1 ,2