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81. 发明授权

US11846695B2 Radio frequency distance determination 有权
公开(公告)号：US11846695B2
公开(公告)日：2023-12-19
申请号：US17538834
申请日：2021-11-30
申请人： Nordic Semiconductor ASA
发明人： Daniel James Ryan , Per Erik Sandgren , Carsten Wulff
IPC分类号： G01S13/08
CPC分类号： G01S13/08
摘要： A method of determining a distance between a radio frequency device and a target is disclosed in which the radio frequency device receives a radio frequency signal from the target. The method comprises determining a time domain channel response from the received radio frequency signal, determining an amplitude of a largest peak in the time domain channel response, determining an amplitude of a second, earlier, peak in the time domain channel response, comparing the second peak amplitude to a threshold based on the largest peak amplitude, identifying the largest peak as a shortest path peak if the second peak amplitude is less than the threshold, identifying the second peak as a shortest path peak if the second peak amplitude is greater than the threshold, and calculating the distance between the radio frequency device and the target based on a time corresponding to the shortest path peak.

82. 发明公开

US20230315456A1 PROCESSING APPARATUS 审中-公开
公开(公告)号：US20230315456A1
公开(公告)日：2023-10-05
申请号：US18020404
申请日：2021-08-10
申请人： Nordic Semiconductor ASA
发明人： Jean-Baptiste BRELOT , Torbjørn Viem NESS , Frode PEDERSEN
IPC分类号： G06F9/30
CPC分类号： G06F9/30101 , G06F9/30123
摘要： A processing apparatus has a processor comprising a plurality of deferred-push processor registers and processor-register control circuitry. The processor-register control circuitry comprises a plurality of status registers, each status register corresponding to a different respective deferred-push register. The processor-register control circuitry is configured to: detect a write of a new value to a register of the deferred-push registers; and determine whether the status register for the deferred-push register has a first value, indicative of an unsaved status for the deferred-push register. The processor-control circuitry is configured, when the status register has the first value, to: read a current value from the deferred-push register before the writing of the new value to the deferred-push register completes; write the current value to a memory; and set the status register for the deferred-push register to a second value, indicative of a saved status for the deferred-push register.

83. 发明授权

US11764770B2 Clock selector circuit 有权
公开(公告)号：US11764770B2
公开(公告)日：2023-09-19
申请号：US17785848
申请日：2020-12-16
申请人： Nordic Semiconductor ASA
发明人： Bartosz Gajda , Frode Pedersen
IPC分类号： H03K3/00 , H03K5/135 , G06F1/08 , H03K3/037 , H03K5/26
CPC分类号： H03K5/135 , G06F1/08 , H03K3/037 , H03K5/26
摘要： A clock selector circuit receives a first input clock signal (CLK1) having a first frequency, and a second input clock signal (CLK2) having a second frequency. A phase difference detector is configured to detect when a phase difference occurs, over time, between the first input clock signal (CLK1) and the second input clock signal (CLK2), determined using when a clock edge crosses zero, and to signal this zero crossing to switching circuitry. The switching circuitry is configured, in response to receiving a zero-crossing signal from the phase difference detector, to detect an edge of opposite type to the predetermined type in the first input clock signal (CLK1) or in the second input clock signal (CLK2), and, in response to detecting said edge of opposite type, to switch an output clock signal (CLK_OUT) between the first input clock signal (CLK1) and the second input clock signal (CLK2).

84. 发明公开

US20230289182A1 HARDWARE ACCELERATOR 审中-公开
公开(公告)号：US20230289182A1
公开(公告)日：2023-09-14
申请号：US18018227
申请日：2021-07-14
申请人： Nordic Semiconductor ASA
发明人： Waqar HUSSAIN
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3001 , G06F9/30134 , G06F9/3877
摘要： A hardware accelerator comprises a direct memory access (DMA) system and an array of processing elements (PEs). Each PE comprises two data inputs and two data outputs and can perform a selectable logical or arithmetic operation. The array comprises configurable interconnects for selectively connecting outputs of the PEs to inputs of the PEs. A first data buffer comprises two or more first-edge cyclic registers, for connecting the DMA system to selected data inputs at a first edge of the PE array. A second data buffer comprises two or more second-edge linear or cyclic shift registers, for connecting selected data outputs of a second edge of the PE array to the DMA system.

85. 发明公开

US20230231592A1 RADIO DEVICE WITH RESONATOR 审中-公开
公开(公告)号：US20230231592A1
公开(公告)日：2023-07-20
申请号：US17926907
申请日：2021-05-28
申请人： Nordic Semiconductor ASA
发明人： Markus LITTOW , Esko NIEMINEN
IPC分类号： H04B1/38 , H03L1/02 , H03L7/197
CPC分类号： H04B1/38 , H03L1/026 , H03L7/1974
摘要： A radio device comprises a radio transceiver, a resonator, a temperature measurement unit, a frequency synthesiser and a processing system. A temperature signal from the temperature measurement unit, representative of a measured temperature of the resonator, is used to determine an estimated frequency offset for the resonator at the measured temperature using a model stored in a memory of the processing system that relates frequency offset to temperature. A periodic signal from the resonator is provided to the frequency synthesizer, which, in dependence on the estimated frequency offset, is used to generate a periodic local signal. The radio transceiver receives a radio signal comprising a periodic component at a received signal frequency. An error value representative of a difference between the received signal frequency and a frequency of the periodic local signal is determined and used to update one or more parameters of the model stored in the memory.

86. 发明公开

US20230225024A1 ILLUMINATING LEDS 审中-公开
公开(公告)号：US20230225024A1
公开(公告)日：2023-07-13
申请号：US18011134
申请日：2021-06-18
申请人： Nordic Semiconductor ASA
发明人： Øystein SMITH , Frode PEDERSEN
IPC分类号： H05B45/10 , H05B45/42 , H05B47/16
CPC分类号： H05B45/10 , H05B45/42 , H05B47/16
摘要： A method of operating a display system consisting of a plurality of light emitting diodes (LEDs) is disclosed. The LEDs are arranged in a plurality of groups and an integrated circuit provides power to the LEDs through a plurality of output pins connected to respective groups. The integrated circuit selectively determines the states of the output pins to illuminate the groups of LEDs in a repeating sequence such that each group is illuminated for a time dependent on a number of groups and a compensation factor. The compensation factor is dependent on at least a number of LEDs in the group.

87. 发明公开

US20230141113A1 DIGITAL RADIO COMMUNICATIONS 审中-公开
公开(公告)号：US20230141113A1
公开(公告)日：2023-05-11
申请号：US17916471
申请日：2021-04-01
申请人： Nordic Semiconductor ASA
发明人： Martin TVERDAL , Sergey KOROTKOV , Johan STRIDKVIST , Rubin GERRITSEN
IPC分类号： H04W74/08 , H04W56/00
CPC分类号： H04W74/0808 , H04W56/004
摘要： A method of operating a digital radio transmitter device in accordance with a predetermined communication protocol defining a transmission timing tolerance. The method comprises: transmitting a plurality of first periodic transmissions in accordance with said predetermined communication protocol having a first period and an inherent timing uncertainty less than said transmission timing tolerance; performing a plurality of second periodic actions with a second period wherein said first and second periods are equal to each other or an integer multiple of each other; and adjusting a timing of one or more of the first periodic transmissions by an amount greater than said inherent timing uncertainty but less than or equal to a difference between said inherent timing uncertainty and said transmission timing tolerance so as to change said first period temporarily by an amount less than or equal to said transmission timing tolerance, thereby changing an offset between said first transmissions and said second actions.

88. 发明授权

US11637550B2 Clock selector circuit 有权
公开(公告)号：US11637550B2
公开(公告)日：2023-04-25
申请号：US17685288
申请日：2022-03-02
申请人： Nordic Semiconductor ASA
发明人： Simon Berg
IPC分类号： H03K5/01 , H03K5/135 , G06F1/08 , H03K4/02
摘要： A clock selector circuit includes a first input for receiving a reference clock signal having a reference frequency, a second input for receiving an offset clock signal having an offset frequency, a clock output for outputting the reference or offset clock signal, and switching circuitry. The switching circuitry includes a switching input and sign detector circuitry that outputs a sign signal indicating whether the reference clock signal is leading the offset clock signal in phase. In response to receiving a switching signal, the switching circuitry detects when like edges of the reference clock signal and the offset clock signal are aligned to within a predetermined tolerance, with the new signal leading the current signal if the offset frequency is lower than the reference frequency, or with the new clock signal trailing the current clock signal if not. In response, the switching circuitry switches to outputting the new clock signal.

89. 发明申请

US20230012226A1 CLOCK SELECTOR CIRCUIT 有权
公开(公告)号：US20230012226A1
公开(公告)日：2023-01-12
申请号：US17785848
申请日：2020-12-16
申请人： Nordic Semiconductor ASA
发明人： Bartosz GAJDA , Frode PEDERSEN
IPC分类号： H03K5/135 , H03K5/26 , H03K3/037 , G06F1/08
摘要： A clock selector circuit receives a first input clock signal (CLK1) having a first frequency, and a second input clock signal (CLK2) having a second frequency. A phase difference detector is configured to detect when a phase difference occurs, over time, between the first input clock signal (CLK1) and the second input clock signal (CLK2), determined using when a clock edge crosses zero, and to signal this zero crossing to switching circuitry. The switching circuitry is configured, in response to receiving a zero-crossing signal from the phase difference detector, to detect an edge of opposite type to the predetermined type in the first input clock signal (CLK1) or in the second input clock signal (CLK2), and, in response to detecting said edge of opposite type, to switch an output clock signal (CLK_OUT) between the first input clock signal (CLK1) and the second input clock signal (CLK2).

90. 发明申请

US20220407530A1 ERROR-FEEDBACK SAR-ADC 有权
公开(公告)号：US20220407530A1
公开(公告)日：2022-12-22
申请号：US17842255
申请日：2022-06-16
申请人： Nordic Semiconductor ASA
发明人： Erlend Strandvik , Harald Garvik
IPC分类号： H03M1/06 , H03M1/00
摘要： Analog to digital conversion circuitry has an input sampling buffer, which has an input sampling capacitor for sampling an analog signal. The conversion circuitry also has a successive-approximation-register analog to digital converter (SAR-ADC) which converts the sampled analog signal to a digital signal. The input sampling buffer has an amplifier and a gain-control capacitor, and has an amplification configuration and an error-feedback configuration. In the amplification configuration, the input sampling capacitor is coupled to the amplifier and gain-control capacitor, with the gain-control capacitor connected in feedback with the amplifier, for applying gain to the sampled analog signal. In the error-feedback configuration, the gain-control capacitor is decoupled from the input sampling capacitor and receives a residue voltage from the SAR-ADC, such that the level of the analog signal determined in the amplification configuration varies depending on the residue voltage received onto the gain-control capacitor in the error-feedback configuration.

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