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81. 发明授权

US06272055B1 Semiconductor memory device 失效
公开(公告)号：US06272055B1
公开(公告)日：2001-08-07
申请号：US09168962
申请日：1998-10-09
申请人： Hideto Hidaka , Mikio Asakura , Kazuyasu Fujishima , Tsukasa Ooishi , Kazutami Arimoto , Shigeki Tomishima , Masaki Tsukude
发明人： Hideto Hidaka , Mikio Asakura , Kazuyasu Fujishima , Tsukasa Ooishi , Kazutami Arimoto , Shigeki Tomishima , Masaki Tsukude
IPC分类号： G11C700
CPC分类号： G11C11/4085 , G11C5/14 , G11C5/147 , G11C7/062 , G11C7/067 , G11C7/12 , G11C7/14 , G11C8/08 , G11C11/4074 , G11C11/4091
摘要： Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss′, and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss′.

82. 发明授权

US06232793B1 Switched backgate bias for FET 有权
标题翻译： FET的开关背栅偏置
公开(公告)号：US06232793B1
公开(公告)日：2001-05-15
申请号：US09195460
申请日：1998-11-18
申请人： Kazutami Arimoto , Masaki Tsukude
发明人： Kazutami Arimoto , Masaki Tsukude
IPC分类号： H03K19185
CPC分类号： H01L27/1203 , H01L27/0218 , H03K19/0016 , H03K2217/0018
摘要： A semiconductor circuit or a MOS-DRAM wherein converting means is provided that converts substrate potential or body bias potential between two values for MOS-FETs in a logic circuit, memory cells, and operating circuit of the MOS-DRAM, thereby raising the threshold voltage of the MOS-FETs when in the standby state and lowering it when in active state. The converting means includes a level shift circuit and a switch circuit. The substrate potential or body bias potential is controlled only of the MOS-FETs which are nonconducting in the standby state; this configuration achieves a reduction in power consumption associated with the potential switching. Furthermore, in a structure where MOS-FETs of the same conductivity type are formed adjacent to each other, MOS-FETs of SOI structure are preferable for better results.
摘要翻译：一种半导体电路或MOS-DRAM，其中提供了转换装置，其将MOS-FET的逻辑电路，存储单元和工作电路中的MOS-FET的两个值之间的衬底电位或体偏置电位转换，从而提高阈值电压的MOS-FET在处于待机状态时，并且在处于活动状态时将其降低。转换装置包括电平移位电路和开关电路。衬底电位或体偏置电位仅受待机状态下不导通的MOS-FET的控制; 该配置实现了与潜在切换相关联的功耗的降低。此外，在相邻形成相同导电类型的MOS-FET的结构中，为了更好的结果，优选SOI结构的MOS-FET。

83. 发明授权

US06191461B1 Semiconductor device including output circuit improved in electrostatic damage resistance 失效
标题翻译：包括输出电路的半导体器件改善了静电损伤电阻
公开(公告)号：US06191461B1
公开(公告)日：2001-02-20
申请号：US09113150
申请日：1998-07-10
申请人： Masaki Tsukude
发明人： Masaki Tsukude
IPC分类号： H01L2362
CPC分类号： H01L27/0266
摘要： A first transistor having a central impurity region connected to a power supply node and outer-side impurity regions connected to an output node and a second transistor having a central impurity region connected to the output node and outer-side impurity regions connected to the power supply node are so arranged that the impurity regions connected to the power supply node are adjacent to or faced to those connected to the output node. The layout area of an output circuit is reduced without reducing electrostatic damage resistance by parasitic field transistors.
摘要翻译：第一晶体管，其具有连接到电源节点的中心杂质区域和连接到输出节点的外侧杂质区域和具有连接到输出节点的中心杂质区域的第二晶体管和连接到电源的外侧杂质区域节点被布置成使得连接到电源节点的杂质区域与连接到输出节点的杂质区域相邻或面对。输出电路的布局面积减小，而不减少寄生场晶体管的静电损伤电阻。

84. 发明授权

US5943273A Semiconductor memory device 失效
公开(公告)号：US5943273A
公开(公告)日：1999-08-24
申请号：US899143
申请日：1997-07-23
申请人： Hideto Hidaka , Mikio Asakura , Kazuyasu Fujishima , Tsukasa Ooishi , Kazutami Arimoto , Shigeki Tomishima , Masaki Tsukude
发明人： Hideto Hidaka , Mikio Asakura , Kazuyasu Fujishima , Tsukasa Ooishi , Kazutami Arimoto , Shigeki Tomishima , Masaki Tsukude
IPC分类号： G11C11/407 , G11C5/14 , G11C7/06 , G11C7/12 , G11C7/14 , G11C8/08 , G11C11/401 , G11C11/4074 , G11C11/408 , G11C11/409 , G11C11/4091 , H01L21/8242 , H01L27/108 , G11C7/00
CPC分类号： G11C11/4085 , G11C11/4074 , G11C11/4091 , G11C5/14 , G11C5/147 , G11C7/062 , G11C7/067 , G11C7/12 , G11C7/14 , G11C8/08
摘要： Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss', and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss'.

85. 发明授权

US5844295A Semiconductor device having a fuse and an improved moisture resistance 失效
标题翻译：具有保险丝和改进的耐湿性的半导体器件
公开(公告)号：US5844295A
公开(公告)日：1998-12-01
申请号：US650695
申请日：1996-05-20
申请人： Masaki Tsukude , Kazutami Arimoto
发明人： Masaki Tsukude , Kazutami Arimoto
IPC分类号： H01L21/60 , H01L21/768 , H01L21/82 , H01L21/8242 , H01L23/485 , H01L23/522 , H01L27/108 , H01L27/02
CPC分类号： H01L27/108 , H01L23/485 , H01L2924/0002
摘要： An interlayer insulating layer is formed to cover a fuse layer. A concave portion is provided on the surface of interlayer insulating layer located directly above fuse layer. A nitride layer as a passivation layer extends on the sidewalls of concave portion. In this way, a semiconductor device is obtained, the device having an improved moisture resistance, and in which a fuse can be easily blown by laser and a design rule of the region adjacent to the fuse can be improved.
摘要翻译：形成层间绝缘层以覆盖熔丝层。在位于熔丝层正上方的层间绝缘层的表面上设置有凹部。作为钝化层的氮化物层在凹部的侧壁上延伸。以这种方式，可以获得半导体器件，该器件具有改善的耐湿性，并且可以通过激光容易地熔断保险丝，并且可以提高与保险丝相邻的区域的设计规则。

86. 发明授权

US5726946A Semiconductor integrated circuit device having hierarchical power source arrangement 失效
公开(公告)号：US5726946A
公开(公告)日：1998-03-10
申请号：US820545
申请日：1997-03-19
申请人： Tadato Yamagata , Kazutami Arimoto , Masaki Tsukude
发明人： Tadato Yamagata , Kazutami Arimoto , Masaki Tsukude
IPC分类号： G11C11/413 , G11C5/14 , G11C7/22 , G11C8/08 , G11C11/407 , G11C11/4074 , G11C11/408 , H01L27/105 , H03K19/00 , G11C7/00
CPC分类号： G11C5/14 , G11C11/4074 , G11C5/147 , G11C7/22 , G11C8/08 , H03K19/0016
摘要： A variable impedance power supply line and a variable impedance ground line supplying voltages VCL1 and VSL1, respectively, are set to a low impedance state in a stand-by cycle and in a row related signal set period, and to a high impedance state in a column circuitry valid time period. Variable impedance power supply line and variable impedance ground line supplying voltages VCL2 and VSL2, respectively, are set to a high impedance state in the stand-by cycle, and low impedance state in the active cycle and in the row related signal reset time period. Inverters operate as operating power supply voltage of voltages VCL1 and VSL2 or voltages VCL2 and VSL1, in accordance with a logic level of an output signal in the stand-by cycle and in the active cycle. Thus a semiconductor memory device is provided in which subthreshold current in the stand-by cycle and active DC current in the active cycle can be reduced.

87. 发明授权

US5696727A Semiconductor memory device provided with sense amplifier capable of high speed operation with low power consumption 失效
标题翻译：具有能够以低功耗高速运行的读出放大器的半导体存储器件
公开(公告)号：US5696727A
公开(公告)日：1997-12-09
申请号：US742119
申请日：1996-10-31
申请人： Masaki Tsukude , Kazutami Arimoto , Shigeki Tomishima
发明人： Masaki Tsukude , Kazutami Arimoto , Shigeki Tomishima
IPC分类号： G11C11/407 , G11C7/06 , G11C11/401 , G11C11/408 , G11C11/409 , G11C11/4091 , G11C11/4096 , H01L21/8242 , H01L27/108 , G11C7/00
CPC分类号： G11C7/065 , G11C11/4091 , G11C11/4096
摘要： A semiconductor memory device includes a memory cell, a word line, a bit line pair having a first bit line and a second bit line complementary to the first bit line, a p type well, first and second source lines, a source line precharge circuit for precharging the first and second source lines, a sense amplifier connected between the first and second bit lines, driven by the first and second source lines and including first and second n channel MOS transistors formed in the p type well and third and fourth p channel MOS transistors, a first sense amplifier enable transistor connected between a power supply potential node and the first source line, a second sense amplifier enable transistor connected between a ground potential node and the second source line, and a switching circuit connected between the first source line and the p type well, and turning on in response to a control signal when the sense amplifier is active.
摘要翻译：半导体存储器件包括存储单元，字线，具有与第一位线互补的第一位线和第二位线的位线对，ap型阱，第一和第二源极线，源极线预充电电路，对第一和第二源极线进行预充电，连接在由第一和第二源极线驱动的第一和第二位线之间的读出放大器，并且包括形成在p型阱中的第一和第二n沟道MOS晶体管以及第三和第四p沟道MOS 晶体管，连接在电源电位节点和第一源极线之间的第一读出放大器使能晶体管，连接在地电位节点和第二源极线之间的第二读出放大器使能晶体管，以及连接在第一源线和 p型良好，并且当感测放大器活动时响应于控制信号而导通。

88. 发明授权

US5694364A Semiconductor integrated circuit device having a test mode for reliability evaluation 失效
标题翻译：具有用于可靠性评估的测试模式的半导体集成电路器件
公开(公告)号：US5694364A
公开(公告)日：1997-12-02
申请号：US779186
申请日：1997-01-06
申请人： Fukashi Morishita , Masaki Tsukude , Kazutami Arimoto
发明人： Fukashi Morishita , Masaki Tsukude , Kazutami Arimoto
IPC分类号： G11C11/407 , G11C5/14 , G11C11/401 , G11C29/00 , G11C29/06 , H01L21/822 , H01L27/04 , G11C7/00
CPC分类号： G11C5/147
摘要： In the normal mode, a first voltage-down converter down-converts an external power supply voltage to provide a large, first internal power supply voltage to the peripheral circuitry via a first internal power supply voltage supplying line, and a second voltage-down converter down-converts the external power supply voltage to provide a smaller, second internal power supply voltage to a memory cell array via a second internal power supply voltage supplying line. This allows fast operation and reduction in power consumption. In conducting a burn-in test, an external power supply voltage supplying line is connected to the first and second internal power supply voltage supplying lines. Thus, the first and second internal power supply voltage supplying lines directly receive the external power supply voltage. This allows an effective burn-in test. In a burn-in test, the first and second voltage-down converters are inactivated.
摘要翻译：在正常模式中，第一降压转换器对外部电源电压进行下变频，以经由第一内部电源电压供应线向外围电路提供大的第一内部电源电压，以及第二降压转换器降低外部电源电压，以经由第二内部电源电压供给线向存储单元阵列提供较小的第二内部电源电压。这允许快速操作和降低功耗。在进行老化试验时，外部电源电压供给线与第一和第二内部电源电压供给线连接。因此，第一和第二内部电源电压供给线直接接收外部电源电压。这允许有效的老化测试。在老化测试中，第一和第二降压转换器失效。

89. 发明授权

US5687123A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5687123A
公开(公告)日：1997-11-11
申请号：US312968
申请日：1994-09-30
申请人： Hideto Hidaka , Mikio Asakura , Kazuyasu Fujishima , Tsukasa Ooishi , Kazutami Arimoto , Shigeki Tomishima , Masaki Tsukude
发明人： Hideto Hidaka , Mikio Asakura , Kazuyasu Fujishima , Tsukasa Ooishi , Kazutami Arimoto , Shigeki Tomishima , Masaki Tsukude
IPC分类号： G11C11/407 , G11C5/14 , G11C7/06 , G11C7/12 , G11C7/14 , G11C8/08 , G11C11/401 , G11C11/4074 , G11C11/408 , G11C11/409 , G11C11/4091 , H01L21/8242 , H01L27/108 , G11C7/00
CPC分类号： G11C11/4085 , G11C11/4074 , G11C11/4091 , G11C5/14 , G11C5/147 , G11C7/062 , G11C7/067 , G11C7/12 , G11C7/14 , G11C8/08
摘要： Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss', and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss'.
摘要翻译：第一和第二晶体管的漏极连接到诸如与确定存储器单元中的电位相关的读出放大器的内部电路的低电平线。第一个晶体管的栅极二极管连接到感测驱动线，其源极接地。第二晶体管在其栅极处接收内部产生的信号，其源极接地。在待机状态下，将感测驱动线的电位设定为比第一晶体管的阈值电压Vthn高于所述字线的低电平，并将其用作虚设GND电位Vss'，而在激活状态下，第二晶体管为导通，以防止感测驱动线从虚拟GND电位Vss'浮起。

90. 发明授权

US5659517A Semiconductor memory device with an improved hierarchical power supply line configuration 失效
标题翻译：具有改进的分层电源线配置的半导体存储器件
公开(公告)号：US5659517A
公开(公告)日：1997-08-19
申请号：US486751
申请日：1995-06-06
申请人： Kazutami Arimoto , Masaki Tsukude
发明人： Kazutami Arimoto , Masaki Tsukude
IPC分类号： G11C11/408 , G11C5/14 , G11C11/407 , G11C11/4074 , G11C11/413 , H01L21/822 , H01L27/04 , H01L27/06 , H03K19/00 , G11C7/00
CPC分类号： G11C11/4074 , G11C5/14 , G11C5/147
摘要： In a semiconductor integrated circuit device, a voltage setting circuit for setting a voltage level on the sub power source voltage line according to a reference voltage from a reference voltage generating circuit, is provided between a main power source voltage line and a sub power source voltage line. While a current consumption at the standby cycle is reduced, increase of the access delay is prevented. The voltage setting circuit includes a differential amplifier for differentially amplifying a voltage on the sub power source line and the reference voltages and a transistor responsive to an output of the differential amplifier for causing a current flow between the main and sub power source lines, or alternatively a diode-connected insulated gate type transistor receiving the reference voltage at a back gate thereof.
摘要翻译：在半导体集成电路装置中，在主电源电压线和副电源电压之间设置用于根据来自基准电压发生电路的基准电压设定副电源电压线上的电压电平的电压设定电路线。虽然在备用周期的电流消耗减少，但是阻止了访问延迟的增加。电压设定电路包括用于差分放大副电源线上的电压和参考电压的差分放大器，以及响应于差分放大器的输出以在主电源线和副电源线之间引起电流的晶体管，或者二极管连接的绝缘栅型晶体管，在其后栅极接收参考电压。

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