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81. 发明授权

US08691673B2 Semiconductor structure with suppressed STI dishing effect at resistor region 有权
标题翻译：在电阻器区域具有抑制的STI凹陷效应的半导体结构
公开(公告)号：US08691673B2
公开(公告)日：2014-04-08
申请号：US13115488
申请日：2011-05-25
申请人： Hak-Lay Chuang , Ming Zhu , Lee-Wee Teo , Bao-Ru Young
发明人： Hak-Lay Chuang , Ming Zhu , Lee-Wee Teo , Bao-Ru Young
IPC分类号： H01L21/00
CPC分类号： H01L27/0629 , H01L21/31055 , H01L21/31111 , H01L21/76224 , H01L28/20 , H01L29/0649
摘要： A method includes forming a first isolation feature of a first width and a second isolation feature of a second width in a substrate, the first width being substantially greater than the second width; forming an implantation mask on the substrate, wherein the implantation mask covers the first isolation feature and exposes the second isolation feature; performing an ion implantation process to the substrate using the implantation mask; and thereafter performing an etching process to the substrate.
摘要翻译：一种方法包括在衬底中形成第一宽度的第一隔离特征和第二宽度的第二隔离特征，第一宽度基本上大于第二宽度; 在所述衬底上形成注入掩模，其中所述注入掩模覆盖所述第一隔离特征并暴露所述第二隔离特征; 使用所述注入掩模对所述衬底进行离子注入工艺; 然后对基板进行蚀刻处理。

82. 发明授权

US08680619B2 Method of fabricating hybrid impact-ionization semiconductor device 有权
标题翻译：制造混合冲击电离半导体器件的方法
公开(公告)号：US08680619B2
公开(公告)日：2014-03-25
申请号：US12725081
申请日：2010-03-16
申请人： Ming Zhu , Lee-Wee Teo , Harry Hak-Lay Chuang
发明人： Ming Zhu , Lee-Wee Teo , Harry Hak-Lay Chuang
IPC分类号： H01L23/62
CPC分类号： H01L29/66484 , H01L21/823807 , H01L29/423 , H01L29/7391
摘要： The present disclosure provides a semiconductor device which includes a semiconductor substrate, a first gate structure disposed over the substrate, the first gate structure including a first gate electrode of a first conductivity type, a second gate structure disposed over the substrate and proximate the first gate structure, the second gate structure including a second gate electrode of a second conductivity type different from the first conductivity type, a first doped region of the first conductivity type disposed in the substrate, the first doped region including a first lightly doped region aligned with a side of the first gate structure, and a second doped region of the second conductivity type disposed in the substrate, the second doped region including a second lightly doped region aligned with a side of the second gate structure.
摘要翻译：本公开提供一种半导体器件，其包括半导体衬底，设置在衬底上的第一栅极结构，第一栅极结构包括第一导电类型的第一栅极电极，设置在衬底上并靠近第一栅极的第二栅极结构所述第二栅极结构包括不同于所述第一导电类型的第二导电类型的第二栅极电极，设置在所述衬底中的所述第一导电类型的第一掺杂区域，所述第一掺杂区域包括与第一导电类型对准的第一轻掺杂区域并且第二导电类型的第二掺杂区域设置在衬底中，第二掺杂区域包括与第二栅极结构的一侧对准的第二轻掺杂区域。

83. 发明申请

US20140048886A1 SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US20140048886A1
公开(公告)日：2014-02-20
申请号：US13586472
申请日：2012-08-15
申请人： Harry-Hak-Lay Chuang , Sin-Hua Wu , Chung-Hau Fei , Ming Zhu , Bao-Ru Young
发明人： Harry-Hak-Lay Chuang , Sin-Hua Wu , Chung-Hau Fei , Ming Zhu , Bao-Ru Young
IPC分类号： H01L21/336 , H01L27/092 , H01L21/8238
CPC分类号： H01L21/823814 , H01L21/26506 , H01L21/26586 , H01L21/26593 , H01L21/324 , H01L21/823807 , H01L27/092 , H01L29/0688 , H01L29/165 , H01L29/41758 , H01L29/6653 , H01L29/66553 , H01L29/66628 , H01L29/66636 , H01L29/7843 , H01L29/7847 , H01L29/7848
摘要： A method of forming a semiconductor device includes forming a gate stack over a substrate, forming an amorphized region in the substrate adjacent to an edge of the gate stack, forming a stress film over the substrate, performing a process to form a dislocation with a pinchoff point in the substrate, removing at least a portion of the dislocation to form a recess cavity with a tip in the substrate, and forming a source/drain feature in the recess cavity.
摘要翻译：一种形成半导体器件的方法包括在衬底上形成栅极叠层，在邻近栅极叠层的边缘的衬底中形成非晶化区域，在衬底上形成应力膜，执行用pinchoff形成位错的工艺在衬底中去除至少一部分位错以在衬底中形成具有尖端的凹腔，并且在凹腔中形成源/漏特征。

84. 发明授权

US08635573B2 Method of fabricating a semiconductor device having a defined minimum gate spacing between adjacent gate structures 有权
标题翻译：制造在相邻栅极结构之间具有限定的最小栅极间距的半导体器件的方法
公开(公告)号：US08635573B2
公开(公告)日：2014-01-21
申请号：US13195628
申请日：2011-08-01
申请人： Hak-Lay Chuang , Ming Zhu , Po-Nien Chen , Bao-Ru Young
发明人： Hak-Lay Chuang , Ming Zhu , Po-Nien Chen , Bao-Ru Young
IPC分类号： G06F17/50 , H01L21/3205
CPC分类号： H01L29/42376 , G06F17/5068 , G06F17/5072 , G06F17/5081 , H01L21/823437 , H01L27/0207 , H01L27/0218 , H01L27/088 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/785 , H01L2223/58
摘要： A device, and method of fabricating and/or designing such a device, including a first gate structure having a width (W) and a length (L) and a second gate structure separated from the first gate structure by a distance greater than: (√{square root over (W*W+L*L)})/10. The second gate structure is a next adjacent gate structure to the first gate structure. A method and apparatus for designing an integrated circuit including implementing a design rule defining the separation of gate structures is also described. In embodiments, the distance of separation is implemented for gate structures that are larger relative to other gate structures on the substrate (e.g., greater than 3 μm2).
摘要翻译：一种器件，以及制造和/或设计这种器件的方法，包括具有宽度（W）和长度（L）的第一栅极结构以及与第一栅极结构分离大于的距离的第二栅极结构： √{平方根（W * W + L * L）}）/ 10。第二栅极结构是与第一栅极结构相邻的下一个栅极结构。还描述了一种用于设计集成电路的方法和装置，包括实现限定栅极结构分离的设计规则。在实施例中，对于相对于衬底上的其它栅极结构（例如，大于3mum2）较大的栅极结构，实现分离距离。

85. 发明授权

US08614484B2 High voltage device with partial silicon germanium epi source/drain 有权
标题翻译：具有部分硅锗外延源/漏极的高压器件
公开(公告)号：US08614484B2
公开(公告)日：2013-12-24
申请号：US12647031
申请日：2009-12-24
申请人： Lee-Wee Teo , Ming Zhu , Harry Hak-Lay Chuang
发明人： Lee-Wee Teo , Ming Zhu , Harry Hak-Lay Chuang
IPC分类号： H01L29/00
CPC分类号： H01L29/0847 , H01L29/0646 , H01L29/165 , H01L29/456 , H01L29/4933 , H01L29/665 , H01L29/66659 , H01L29/7835
摘要： A semiconductor device is provided which includes a semiconductor substrate, a gate structure formed on the substrate, sidewall spacers formed on each side of the gate structure, a source and a drain formed in the substrate on either side of the gate structure, the source and drain having a first type of conductivity, a lightly doped region formed in the substrate and aligned with a side of the gate structure, the lightly doped region having the first type of conductivity, and a barrier region formed in the substrate and adjacent the drain. The barrier region is formed by doping a dopant of a second type of conductivity different from the first type of conductivity.
摘要翻译：提供一种半导体器件，其包括半导体衬底，形成在衬底上的栅极结构，形成在栅极结构的每一侧上的侧壁间隔物，形成在栅极结构的任一侧上的衬底中的源极和漏极，源极和具有第一类型的导电性的漏极，形成在衬底中并与栅极结构的一侧对齐的轻掺杂区域，具有第一类型导电性的轻掺杂区域和形成在衬底中并邻近漏极的势垒区域。阻挡区域通过掺杂不同于第一类型导电性的第二类型导电性的掺杂剂而形成。

86. 发明申请

US20130323893A1 Methods for Forming MOS Devices with Raised Source/Drain Regions 有权
标题翻译：用于形成源/漏区MOS器件的方法
公开(公告)号：US20130323893A1
公开(公告)日：2013-12-05
申请号：US13486240
申请日：2012-06-01
申请人： Harry-Hak-Lay Chuang , Sin-Hua Wu , Chung-Hau Fei , Ming Zhu , Bao-Ru Young , Yen-Ru Lee , Chii-Horng Li , Tze-Liang Lee
发明人： Harry-Hak-Lay Chuang , Sin-Hua Wu , Chung-Hau Fei , Ming Zhu , Bao-Ru Young , Yen-Ru Lee , Chii-Horng Li , Tze-Liang Lee
IPC分类号： H01L21/8238
CPC分类号： H01L27/1116 , H01L21/823807 , H01L21/823814
摘要： A method includes forming a first gate stack of a first device over a semiconductor substrate, and forming a second gate stack of a second MOS device over the semiconductor substrate. A first epitaxy is performed to form a source/drain stressor for the second MOS device, wherein the source/drain stressor is adjacent to the second gate stack. A second epitaxy is performed to form a first silicon layer and a second silicon layer simultaneously, wherein the first silicon layer is over a first portion of the semiconductor substrate, and is adjacent the first gate stack. The second silicon layer overlaps the source/drain stressor.
摘要翻译：一种方法包括在半导体衬底上形成第一器件的第一栅极堆叠，以及在半导体衬底上形成第二MOS器件的第二栅极堆叠。执行第一外延以形成用于第二MOS器件的源/漏应力源，其中源极/漏极应力器与第二栅极堆叠相邻。执行第二外延以同时形成第一硅层和第二硅层，其中第一硅层位于半导体衬底的第一部分之上并且与第一栅极堆叠相邻。第二硅层与源极/漏极应力源重叠。

87. 发明授权

US08586428B2 Interconnection structure for N/P metal gates 有权
标题翻译： N / P金属门互连结构
公开(公告)号：US08586428B2
公开(公告)日：2013-11-19
申请号：US13618421
申请日：2012-09-14
申请人： Han-Guan Chew , Ming Zhu , Lee-Wee Teo , Harry-Hak-Lay Chuang
发明人： Han-Guan Chew , Ming Zhu , Lee-Wee Teo , Harry-Hak-Lay Chuang
IPC分类号： H01L21/8238
CPC分类号： H01L21/768 , H01L21/28088 , H01L21/823842 , H01L21/823871 , H01L29/4966 , H01L29/66545 , H01L29/66606 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： This description relates to a method for fabricating an interconnection structure in a complementary metal-oxide-semiconductor (CMOS). The method includes forming a first opening in a dielectric layer over a substrate and partially filling the first opening with a second work-function metal layer, wherein a top surface of the second work-function metal layer is below a top surface of the first opening. The method further includes forming a second opening adjoining the first opening in the dielectric layer over the substrate and depositing a first work-function metal layer in the first and second openings, whereby the first work-function metal layer is over the second work-function metal layer in the first opening. The method further includes depositing a signal metal layer over the first work-function metal layer in the first and second openings and planarizing the signal metal layer.
摘要翻译：该描述涉及用于制造互补金属氧化物半导体（CMOS）中的互连结构的方法。该方法包括在基板上形成电介质层中的第一开口，并用第二功函数金属层部分地填充第一开口，其中第二功函数金属层的顶表面在第一开口的顶表面下方。所述方法还包括在所述基板上形成邻近所述电介质层中的所述第一开口的第二开口，并且在所述第一和第二开口中沉积第一功函数金属层，由此所述第一功函数金属层超过所述第二功函数金属层在第一个开口。该方法还包括在第一和第二开口中的第一功函数金属层上方沉积信号金属层并平坦化信号金属层。

88. 发明申请

US20130270647A1 STRUCTURE AND METHOD FOR NFET WITH HIGH K METAL GATE 审中-公开
公开(公告)号：US20130270647A1
公开(公告)日：2013-10-17
申请号：US13448846
申请日：2012-04-17
申请人： Ming Zhu , Jin-Aun Ng , Chi-Wen Liu
发明人： Ming Zhu , Jin-Aun Ng , Chi-Wen Liu
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/022 , H01L21/02337 , H01L21/02362 , H01L21/28008 , H01L21/823842 , H01L21/823857 , H01L29/165 , H01L29/4958 , H01L29/517 , H01L29/66545 , H01L29/66636 , H01L29/7848
摘要： The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; a n-type filed effect transistor (nFET) formed on the semiconductor substrate and having a first gate stack including a high k dielectric layer, a capping layer on the high k dielectric layer, a p work function metal on the capping layer, and a polysilicon layer on the p work function metal; and a p-type filed effect transistor (pFET) formed on the semiconductor substrate and having a second gate stack including the high k dielectric layer, the p work function metal on the high k dielectric layer, and a metal material on the p work function metal.

89. 发明授权

US08472212B2 Resonant converting device, and control module and method for controlling a resonant converter 有权
标题翻译：谐振转换装置，以及用于控制谐振转换器的控制模块和方法
公开(公告)号：US08472212B2
公开(公告)日：2013-06-25
申请号：US12890921
申请日：2010-09-27
申请人： Ming-Zhu Li , Jing-Yan Li , Qing-Lin Zhao , Zhi-Hong Ye , Chun-Lin Zhang
发明人： Ming-Zhu Li , Jing-Yan Li , Qing-Lin Zhao , Zhi-Hong Ye , Chun-Lin Zhang
IPC分类号： H02M3/335
CPC分类号： H02M3/33515 , H02M3/33592 , Y02B70/1433 , Y02B70/1475
摘要： A method for controlling operation of a resonant converter is to be implemented by a control module that generates a drive signal for controlling a power switch of the resonant converter to thereby control an output voltage and an output current provided by the resonant converter to a load. The method includes: (A) configuring the control module to determine if the load is operating in a first mode or a second mode; (B) configuring the control module to generate the drive signal according to the output voltage when the control module determines that the load is operating in the first mode; and (C) configuring the control module to generate the drive signal according to the output current when the control module determines that the load is operating in the second mode.
摘要翻译：用于控制谐振转换器的操作的方法将通过产生用于控制谐振转换器的功率开关的驱动信号的控制模块来实现，从而控制由谐振转换器提供的负载的输出电压和输出电流。该方法包括：（A）配置控制模块以确定负载是否以第一模式或第二模式运行; （B）当控制模块确定负载以第一模式运行时，配置控制模块以根据输出电压产生驱动信号; 以及（C）当所述控制模块确定所述负载在所述第二模式下运行时，配置所述控制模块以根据所述输出电流产生所述驱动信号。

90. 发明申请

US20130154021A1 ENHANCED GATE REPLACEMENT PROCESS FOR HIGH-K METAL GATE TECHNOLOGY 有权
标题翻译：用于高K金属门技术的增强门更换过程
公开(公告)号：US20130154021A1
公开(公告)日：2013-06-20
申请号：US13328382
申请日：2011-12-16
申请人： Hak-Lay Chuang , Ming Zhu
发明人： Hak-Lay Chuang , Ming Zhu
IPC分类号： H01L27/092 , H01L21/28
CPC分类号： H01L29/66545 , H01L21/02186 , H01L21/02192 , H01L21/3212 , H01L21/823842 , H01L21/823857
摘要： The present disclosure provides a method of fabricating a semiconductor device. A high-k dielectric layer is formed over a substrate. A first capping layer is formed over a portion of the high-k dielectric layer. A second capping layer is formed over the first capping layer and the high-k dielectric layer. A dummy gate electrode layer is formed over the second capping layer. The dummy gate electrode layer, the second capping layer, the first capping layer, and the high-k dielectric layer are patterned to form an NMOS gate and a PMOS gate. The NMOS gate includes the first capping layer, and the PMOS gate is free of the first capping layer. The dummy gate electrode layer of the PMOS gate is removed, thereby exposing the second capping layer of the PMOS gate. The second capping layer of the PMOS gate is transformed into a third capping layer.
摘要翻译：本公开提供了制造半导体器件的方法。在衬底上形成高k电介质层。在高k电介质层的一部分上形成第一覆盖层。在第一覆盖层和高k电介质层上形成第二覆盖层。在第二盖层上形成虚拟栅电极层。对虚拟栅极电极层，第二覆盖层，第一覆盖层和高k电介质层进行构图以形成NMOS栅极和PMOS栅极。 NMOS栅极包括第一覆盖层，PMOS栅极不含第一覆盖层。去除PMOS栅极的伪栅极电极层，从而暴露PMOS栅极的第二覆盖层。 PMOS栅极的第二覆盖层被转换成第三覆盖层。

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