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    • 81. 发明申请
    • MEMORY WITH DATA LATCHING CIRCUIT INCLUDING A SELECTOR
    • 具有数据连接电路的存储器,包括一个选择器
    • US20060203575A1
    • 2006-09-14
    • US11079726
    • 2005-03-14
    • Jonghee Han
    • Jonghee Han
    • G11C7/00
    • G11C7/1078G11C7/1087G11C7/1093G11C2207/107
    • A circuit for latching data into a memory includes a receiver, a delay, and a selector. The receiver is configured for receiving a data signal, and the delay is configured to delay the data signal to provide a delayed data signal. The selector is configured to receive the delayed data signal, a data strobe signal, and an inverted data strobe signal and provide a first strobe signal and a second strobe signal in response to the delayed data signal, the data strobe signal, and the inverted data strobe signal. Rising edge data is latched into the memory in response to the first strobe signal and falling edge data is latched into the memory in response to the second strobe signal.
    • 用于将数据锁存到存储器中的电路包括接收器,延迟器和选择器。 接收器被配置为用于接收数据信号,并且延迟被配置为延迟数据信号以提供延迟的数据信号。 选择器被配置为接收延迟数据信号,数据选通信号和反相数据选通信号,并响应于延迟的数据信号,数据选通信号和反相数据提供第一选通信号和第二选通信号 频闪信号。 响应于第一选通信号,上升沿数据被锁存到存储器中,并且响应于第二选通信号将下降沿数据锁存到存储器中。