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81. 发明授权

US06548875B2 Sub-tenth micron misfet with source and drain layers formed over source and drains, sloping away from the gate 失效
标题翻译：次级十分之一误差，源极和漏极层形成在源极和漏极之间，远离栅极倾斜
公开(公告)号：US06548875B2
公开(公告)日：2003-04-15
申请号：US09798924
申请日：2001-03-06
申请人： Akira Nishiyama
发明人： Akira Nishiyama
IPC分类号： H01L2978
CPC分类号： H01L21/76897 , H01L21/28562 , H01L21/823835 , H01L21/823842 , H01L29/045 , H01L29/47 , H01L29/665 , H01L29/66545 , H01L29/66628 , H01L29/7834
摘要： A semiconductor device having a low channel resistance without degrading transistor characteristics even for the 0.1 &mgr;m generation or later, and also: a manufacturing method of the device. The method includes fabricating source/drain electrodes and a gate electrode without using selective metal growth methods. Further, after forming the gate electrode, a semiconductor film is temporarily formed selectively in source/drain regions. A dielectric film is next deposited on the substrate and then, the surface is etched by chemical/mechanical polish (CMP) techniques to the extent that the semiconductor film is exposed on the surface. The semiconductor film is then partly etched until its midway portion along the thickness is removed. Thereafter, a desired metal or silicide is deposited on the entire surface. Next, CMP etching is performed to form electrodes, while letting the electrodes reside on or over the source/drain semiconductor layers and a gate insulation layer.
摘要翻译：具有低通道电阻而不降低晶体管特性的半导体器件，即使是0.1μm产生或更迟，以及该器件的制造方法。该方法包括在不使用选择性金属生长方法的情况下制造源/漏电极和栅电极。此外，在形成栅电极之后，半导体膜在源极/漏极区域中暂时选择性地形成。接着在衬底上沉积电介质膜，然后通过化学/机械抛光（CMP）技术对表面进行蚀刻，使得半导体膜暴露在表面上。然后半导体膜被部分蚀刻，直到其沿着厚度的中间部分被去除。此后，在整个表面上沉积所需的金属或硅化物。接下来，进行CMP蚀刻以形成电极，同时使电极驻留在源极/漏极半导体层上或栅极绝缘层上方。

82. 发明授权

US06472544B1 Process for the preparation of optically active 2-[6-hydroxymethyl)-1,3-dioxan-4yl]acetic acid derivatives 有权
标题翻译：制备光学活性2-Ä6-（羟甲基）-1,3-二恶烷-4-基乙酸衍生物的方法
公开(公告)号：US06472544B1
公开(公告)日：2002-10-29
申请号：US09509998
申请日：2000-08-16
申请人： Noriyuki Kizaki , Yukio Yamada , Yoshihiko Yasohara , Akira Nishiyama , Makoto Miyazaki , Masaru Mitsuda , Takeshi Kondo , Noboru Ueyama , Kenji Inoue
发明人： Noriyuki Kizaki , Yukio Yamada , Yoshihiko Yasohara , Akira Nishiyama , Makoto Miyazaki , Masaru Mitsuda , Takeshi Kondo , Noboru Ueyama , Kenji Inoue
IPC分类号： C07D31906
CPC分类号： C07D319/06 , C07B2200/07 , C07C67/343 , C07C253/30 , C12P7/62 , C07C69/716 , C07C255/21
摘要： This invention provides a process for producing optically active 2-[6-(hydroxymethyl)-1,3-dioxan-4-yl]acetic acid derivatives, which are of value as intermediates of drugs, from inexpensive starting materials without using any special equipment such as that required for super-low temperature reactions. A process for producing optically active 2-[6-(hydroxymethyl)-1,3-dioxan-4-yl]acetic acid derivatives which comprises reacting an acetic acid derivative at a temperature of not less than −30° C. with an enolate prepared by permitting either a base or a metal having a valency of 0 to act on the derivative to produce a hydroxyoxohexanoic acid derivative, reducing this compound with the aid of a strain of microorganism to provide a halomethyldioxanylacetic acid derivative, treating this compound with an acetalizing agent in the presence of an acid catalyst to provide a halomethyldioxanylacetic acid derivative, reacted with an acyloxylating agent to provide a acyloxymethyldioxanylacetic acid derivative, and subjecting this compound to solvolysis in the presence of a base.
摘要翻译：本发明提供了从廉价起始原料生产具有价值作为药物中间体的光学活性的2- [6-（羟甲基）-1,3-二恶烷-4-基]乙酸衍生物的方法，而不使用任何特殊设备例如超低温反应所需的方法。一种制备光学活性的2- [6-（羟甲基）-1,3-二恶烷-4-基]乙酸衍生物的方法，其包括在不是的温度下使乙酸衍生物反应小于-30℃，通过使碱金属或化合价为0的金属作用于衍生物以制备羟基氧代己酸衍生物而制备的烯醇化物，借助于微生物菌株还原该化合物以提供卤甲基二恶烷基乙酸衍生物，在酸催化剂存在下用缩醛化剂处理该化合物，得到卤代甲基二恶烷基乙酸衍生物，与酰氧基化剂反应，得到酰氧基甲基二恶烷基乙酸在碱的存在下，将该化合物施用于溶剂分解。

83. 发明授权

US06207486B1 Semiconductor device and a method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06207486B1
公开(公告)日：2001-03-27
申请号：US09151401
申请日：1998-09-11
申请人： Akira Nishiyama
发明人： Akira Nishiyama
IPC分类号： H01L218238
CPC分类号： H01L21/76823 , H01L21/28568 , H01L21/76843 , H01L21/76852 , H01L21/76855
摘要： An object of the present invention is to provide a semiconductor device manufacturing method capable of facilitating achievement of reliable electrical connections between an electrode and a wiring layer in different layers or between wiring layers therein. In accordance with one aspect of the present invention, a semiconductor device manufacturing method includes the steps of forming an element isolation region 51 on one main surface of a semiconductor substrate 50, forming a gate electrode 53, forming source and drain electrodes 56, forming an insulator nitride film 57 on the main surface of the semiconductor substrate 50, forming an interlayer insulator 58 with more than one contact hole H, converting part of the insulator nitride film 57 at the bottom of the contact hole H into a conductive nitride film 61 that is higher in bonding energy than the insulative nitride, and forming wiring layer 62 connected to the source/drain electrodes 56 through the conductive nitride film 61.
摘要翻译：本发明的一个目的是提供一种能够有助于实现电极和不同层之间或布线层之间的布线层之间的可靠电连接的半导体器件制造方法。根据本发明的一个方面，半导体器件制造方法包括以下步骤：在半导体衬底50的一个主表面上形成元件隔离区域51，形成栅电极53，形成源极和漏电极56，在半导体衬底的主表面上形成绝缘体氮化物膜57 如图50所示，形成具有多于一个接触孔H的层间绝缘体58，将接触孔H的底部的绝缘体氮化物膜57的一部分转换为与绝缘氮化物结合能力高的导电氮化物膜61，并形成通过导电氮化物膜61连接到源/漏电极56的布线层62。

84. 发明授权

US08752820B2 Envelope warpage correcting device 有权
标题翻译：信封翘曲矫正装置
公开(公告)号：US08752820B2
公开(公告)日：2014-06-17
申请号：US13361493
申请日：2012-01-30
申请人： Akira Nishiyama
发明人： Akira Nishiyama
IPC分类号： B65H5/00
CPC分类号： B41J13/12
摘要： An envelope warpage correcting device includes a sheet feeding portion, a correction means and a control portion. The sheet feeding portion feeds envelopes one-by-one in a state where the envelopes are stacked on a sheet feed table and a rear end portion opposite to a flap portion formed in a front end portion of each of the envelopes is set to a leading portion in a sheet feed direction. The correction means corrects warpage occurring at a side of the rear end portion of the envelope fed by the sheet feeding portion. The control portion controls processing for correcting the warpage occurring at the side of the rear end portion by the correcting portion at certain timing according to an attribution of the envelope.
摘要翻译：信封翘曲校正装置包括片材馈送部分，校正装置和控制部分。片材进给部分在信封堆叠在供纸台上的状态下一个接一个地进给信封，并且与形成在每个信封的前端部分中的折片部分相对的后端部分被设置为前导部分在片材进给方向上。校正装置校正在由送纸部分供给的信封的后端部的一侧发生的翘曲。控制部根据信封的属性来控制在某一定时由校正部校正在后端部侧的翘曲的处理。

85. 发明授权

US08174080B2 Semiconductor device 有权
公开(公告)号：US08174080B2
公开(公告)日：2012-05-08
申请号：US13184159
申请日：2011-07-15
申请人： Reika Ichihara , Yoshinori Tsuchiya , Masato Koyama , Akira Nishiyama
发明人： Reika Ichihara , Yoshinori Tsuchiya , Masato Koyama , Akira Nishiyama
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/823857 , H01L21/823462
摘要： A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.

86. 发明授权

US07884416B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US07884416B2
公开(公告)日：2011-02-08
申请号：US11853415
申请日：2007-09-11
申请人： Hiroshi Watanabe , Akira Nishiyama
发明人： Hiroshi Watanabe , Akira Nishiyama
IPC分类号： H01L29/788
CPC分类号： H01L21/28273 , G04F10/10 , G04F13/00 , G11C16/0433 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A semiconductor integrated circuit according to an example of the present invention includes a semiconductor substrate, an element isolation insulating layer formed in a surface region of the semiconductor substrate, and first and second MIS type devices isolated from each other by the element isolation insulating layer and formed in adjacent first and second element regions in a second direction orthogonal to a first direction. Each of the first and second MIS type devices has a stack gate structure having a floating gate and a control gate electrode. The first MIS type device functions as an aging device, and the second MIS type device functions as a control device which controls an electric charge retention characteristic of the aging device.
摘要翻译：根据本发明的实施例的半导体集成电路包括半导体衬底，形成在半导体衬底的表面区域中的元件隔离绝缘层以及通过元件隔离绝缘层彼此隔离的第一和第二MIS型器件，以及在与第一方向正交的第二方向上形成在相邻的第一和第二元件区域中。第一和第二MIS型器件中的每一个具有具有浮置栅极和控制栅极电极的堆叠栅极结构。第一MIS型装置用作老化装置，第二MIS型装置用作控制老化装置的电荷保持特性的控制装置。

87. 发明授权

US07728394B2 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07728394B2
公开(公告)日：2010-06-01
申请号：US12232079
申请日：2008-09-10
申请人： Masato Koyama , Reika Ichihara , Yoshinori Tsuchiya , Yuuichi Kamimuta , Akira Nishiyama
发明人： Masato Koyama , Reika Ichihara , Yoshinori Tsuchiya , Yuuichi Kamimuta , Akira Nishiyama
IPC分类号： H00L29/79
CPC分类号： H01L21/823842
摘要： A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 80% or more, and an n-channel MIS transistor formed on a p-type well on the substrate, having a second gate dielectric and a second gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 60% or less.
摘要翻译：半导体器件包括衬底，形成在衬底上的n型阱上的p沟道MIS晶体管，具有形成在其上并由Ta-C合金形成的第一栅极电介质和第一栅电极，其中晶体取向比例膜厚方向[TaC（111）面/ {TaC（111）面+ TaC（200）面}]的TaC（111）面为80％以上，n型沟道MIS晶体管形成在p- 在基板上良好地形成具有形成在其上的第二栅极电介质和第二栅电极，并且由TaC（111）在膜厚度方向[TaC（111）面/ {TaC（111）面+ TaC（200）面}]为60％以下。

88. 发明授权

US07632728B2 Method of forming TaC gate electrodes with crystal orientation ratio defining the work function 有权
标题翻译：形成具有定义功函数的晶体取向比的TaC栅电极的方法
公开(公告)号：US07632728B2
公开(公告)日：2009-12-15
申请号：US12232080
申请日：2008-09-10
申请人： Masato Koyama , Reika Ichihara , Yoshinori Tsuchiya , Yuuichi Kamimuta , Akira Nishiyama
发明人： Masato Koyama , Reika Ichihara , Yoshinori Tsuchiya , Yuuichi Kamimuta , Akira Nishiyama
IPC分类号： H01L29/78 , H01L29/04 , H01L21/8234 , H01L21/8238
CPC分类号： H01L21/823842
摘要： A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 80% or more, and an n-channel MIS transistor formed on a p-type well on the substrate, having a second gate dielectric and a second gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 60% or less.
摘要翻译：半导体器件包括衬底，形成在衬底上的n型阱上的p沟道MIS晶体管，具有形成在其上并由Ta-C合金形成的第一栅极电介质和第一栅电极，其中晶体取向比例膜厚方向[TaC（111）面/ {TaC（111）面+ TaC（200）面}]的TaC（111）面为80％以上，n型沟道MIS晶体管形成在p- 在基板上良好地形成具有形成在其上的第二栅极电介质和第二栅电极，并且由TaC（111）在膜厚度方向[TaC（111）面/ {TaC（111）面+ TaC（200）面}]为60％以下。

89. 发明申请

US20090075464A1 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20090075464A1
公开(公告)日：2009-03-19
申请号：US12232080
申请日：2008-09-10
申请人： Masato Koyama , Reika Ichihara , Yoshinori Tsuchiya , Yuuichi Kamimuta , Akira Nishiyama
发明人： Masato Koyama , Reika Ichihara , Yoshinori Tsuchiya , Yuuichi Kamimuta , Akira Nishiyama
IPC分类号： H01L21/28
CPC分类号： H01L21/823842
摘要： A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 80% or more, and an n-channel MIS transistor formed on a p-type well on the substrate, having a second gate dielectric and a second gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 60% or less.
摘要翻译：半导体器件包括衬底，形成在衬底上的n型阱上的p沟道MIS晶体管，具有形成在其上并由Ta-C合金形成的第一栅极电介质和第一栅电极，其中晶体取向比例膜厚方向[TaC（111）面/ {TaC（111）面+ TaC（200）面}]的TaC（111）面为80％以上，n型沟道MIS晶体管形成在p- 在基板上良好地形成具有形成在其上的第二栅极电介质和第二栅电极，并且由TaC（111）在膜厚度方向[TaC（111）面/ {TaC（111）面+ TaC（200）面}]为60％以下。

90. 发明申请

US20090072330A1 Semiconductor device and manufacturing method thereof 有权
公开(公告)号：US20090072330A1
公开(公告)日：2009-03-19
申请号：US12232078
申请日：2008-09-10
申请人： Masato Koyama , Reika Ichihara , Yoshinori Tsuchiya , Yuuichi Kamimuta , Akira Nishiyama
发明人： Masato Koyama , Reika Ichihara , Yoshinori Tsuchiya , Yuuichi Kamimuta , Akira Nishiyama
IPC分类号： H01L29/78
CPC分类号： H01L21/823842
摘要： A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 80% or more, and an n-channel MIS transistor formed on a p-type well on the substrate, having a second gate dielectric and a second gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 60% or less.

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