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81. 发明授权

US09544240B1 MTU discovery over multicast path using bit indexed explicit replication 有权
标题翻译：通过使用位索引显式复制的组播路径的MTU发现
公开(公告)号：US09544240B1
公开(公告)日：2017-01-10
申请号：US14798297
申请日：2015-07-13
申请人： Telefonaktiebolaget L M Ericsson (publ)
发明人： Antoni Przygienda , Gregory Mirsky
IPC分类号： H04L12/28 , H04L12/805 , H04L12/18
CPC分类号： H04L12/18 , H04L12/1863 , H04L12/1886 , H04L45/586 , H04L47/15 , H04L47/365
摘要： A method and system provides for path maximum transmission unit (PMTU) discovery (PMTUD) for a multicast distribution implemented in a network using bit indexed explicit replication (BIER) architecture. The network has a set of bit forwarding routers (BFRs) that form a BIER domain including at least one ingress BFR (BFIR) and a set of egress BFRs (BFERs). The method improves efficiency of the PMTUD by limiting probe packet traffic. The method includes selecting a BFER from the set of BFERs in the BIER domain to be processed, generating a probe packet to the selected BFER using a current MTU, sending the probe packet to the selected BFER, and updating the current MTU and adding BFERs identified by a response to the probe packet to the set of BFERs in the BIER domain to be processed.
摘要翻译：一种方法和系统提供了使用位索引显性复制（BIER）架构在网络中实现的组播分发的路径最大传输单元（PMTU）发现（PMTUD）。该网络具有形成包括至少一个入口BFR（BFIR）和一组出口BFR（BFER）的BIER域的一组位转发路由器（BFR）。该方法通过限制探测分组流量来提高PMTUD的效率。该方法包括从要处理的BIER域中的一组BFER中选择BFER，使用当前MTU向所选BFER生成探测包，将探测包发送到所选BFER，更新当前MTU并添加已识别的BFER 通过对要处理的BIER域中的BFER集合的探测分组的响应。

82. 发明授权

US09514093B2 Method and apparatus for stacking core and uncore dies having landing slots 有权
标题翻译：用于堆叠具有着陆槽的芯和裸芯片的方法和装置
公开(公告)号：US09514093B2
公开(公告)日：2016-12-06
申请号：US14498353
申请日：2014-09-26
申请人： INTEL CORPORATION
发明人： Stefan Rusu
IPC分类号： G06F15/76 , H01L25/065
CPC分类号： H01L25/18 , G06F12/1045 , G06F15/76 , G06F2212/1008 , G06F2212/283 , G06F2212/455 , G06F2212/608 , G06F2212/68 , H01L23/481 , H01L23/544 , H01L25/0657 , H01L25/50 , H01L2223/54426 , H01L2225/06541 , H01L2225/06593 , H01L2924/0002 , H01L2924/00
摘要： An apparatus and method are described for stacking a plurality of cores. For example, one embodiment of an apparatus comprises: a package; an uncore die mounted on the package, the uncore die comprising a plurality of exposed landing slots, each landing slot including an inter-die interface usable to connect vertically to a cores die, the uncore die including a plurality of uncore components usable by cores within the cores die including a memory controller component, a level 3 (L3) cache, a system memory or system memory interface, and a core interconnect fabric or bus; and a first cores die comprising a first plurality of cores, the cores spaced on the first cores die to correspond to all or a first subset of the landing slots on the uncore die, each of the cores having an inter-die interface positioned to be communicatively coupled to a corresponding inter-die interface within a landing slot on the uncore die when the first cores die is vertically coupled on top of the uncore die, wherein the communicative coupling between the inter-die interface of a core and the inter-die interface of its corresponding landing slot communicatively couples the core to the uncore components of the uncore die.
摘要翻译：描述了用于堆叠多个核的装置和方法。例如，装置的一个实施例包括：包装; 安装在所述封装上的非芯模，所述裸芯包括多个暴露的着陆槽，每个着陆槽包括可垂直地连接到芯模的管芯间界面，所述裸芯包括多个可由核心内部的芯部核心包括存储器控制器组件，级别3（L3）高速缓存，系统存储器或系统存储器接口以及核心互连结构或总线; 以及包括第一多个芯的第一芯芯，所述芯在所述第一芯上分开，以对应于所述裸芯上的所述着陆槽的全部或第一子集，所述芯中的每一个具有定位成为当所述第一芯管芯垂直耦合在所述裸芯片的顶部上时，在所述裸芯片上的着陆槽内通信地耦合到相应的晶片间界面，其中，所述芯体的晶片间界面与所述晶片间的交流耦合其对应的着陆槽的接口将核心通信地耦合到裸芯片的非零部件。

83. 发明授权

US09497661B2 Implementing EPC in a cloud computer with openflow data plane 有权
标题翻译：在具有开放数据平面的云计算机中实现EPC
公开(公告)号：US09497661B2
公开(公告)日：2016-11-15
申请号：US14486896
申请日：2014-09-15
申请人： Telefonaktiebolaget L M Ericsson (publ)
发明人： James Kempf , Bengt E. Johansson , Sten Pettersson , Tord K. Nilsson , Harald Lüning
IPC分类号： H04W28/02 , H04W24/02 , H04W24/04 , H04L12/24 , H04L12/26 , H04L12/851 , H04W88/12
CPC分类号： H04W28/0268 , H04L41/0695 , H04L43/0882 , H04L43/16 , H04L47/2441 , H04W24/02 , H04W24/04 , H04W88/12
摘要： A method implements a control plane of an evolved packet core (EPC) of a long term evolution (LTE) network in a cloud computing system. A cloud manager monitors resource utilization of each control plane module and the control plane traffic handled by each control plane module. The cloud manager detects a threshold level of resource utilization or traffic load for one of the plurality of control plane modules of the EPC. A new control plane module is initialized as a separate virtual machine by the cloud manager in response to detecting the threshold level. The new control plane module signals the plurality of network elements in the data plane to establish flow rules and actions to establish differential routing of flows in the data plane using the control protocol, wherein flow matches are encoded using an extensible match structure in which the flow match is encoded as a type-length-value (TLV).
摘要翻译：一种方法实现云计算系统中长期演进（LTE）网络的演进分组核心（EPC）的控制平面。云管理器监视每个控制平面模块和每个控制平面模块处理的控制平面流量的资源利用率。云管理器检测EPC的多个控制平面模块之一的资源利用率或流量负载的阈值水平。响应于检测到阈值水平，云管理器将新的控制平面模块初始化为单独的虚拟机。新的控制平面模块向数据平面中的多个网络元件发信号以建立流规则和动作，以使用控制协议在数据平面中建立流的差分路由，其中使用可扩展匹配结构对流匹配进行编码，其中流匹配被编码为类型长度值（TLV）。

84. 发明授权

US09478204B2 Sub-harmonic mixer 有权
标题翻译：次谐波混频器
公开(公告)号：US09478204B2
公开(公告)日：2016-10-25
申请号：US14425921
申请日：2012-09-04
申请人： Mingquan Bao
发明人： Mingquan Bao
IPC分类号： H04M1/00 , G10H1/32 , H03D7/02 , H03D7/12
CPC分类号： G10H1/32 , H03D7/02 , H03D7/12
摘要： A sub-harmonic mixer comprising first and second input ports, and an output port, and arranged to output products of signals applied at the input ports. The sub-harmonic mixer comprises a first stage a second stage arranged in series with each other, with the input ports of the sub-harmonic mixer being input ports of the first stage, and the output port of the sub-harmonic mixer being an output port of the second stage. An output port of the first stage is connected to an input port of the second stage. The first stage is arranged to generate a fundamental product and a first third order intermodulation distortion product in-phase with each other. The second stage is arranged to generate a second third order intermodulation distortion product in anti-phase to the fundamental product generated by the second stage.
摘要翻译：包括第一和第二输入端口的子谐波混合器和输出端口，并被布置成输出在输入端口处施加的信号的产物。子谐波混频器包括第一级，第二级彼此串联布置，子谐波混合器的输入端口是第一级的输入端口，并且子谐波混频器的输出端口是输出端第二阶段港第一级的输出端口连接到第二级的输入端口。第一级被设置为产生彼此同相的基本乘积和第一三阶互调失真乘积。第二级被布置为产生与第二级产生的基本产品相反的第二级三阶互调失真产物。

85. 发明授权

US09438472B2 Extended remote LFA fast reroute 有权
标题翻译：扩展远程LFA快速重路由
公开(公告)号：US09438472B2
公开(公告)日：2016-09-06
申请号：US13946827
申请日：2013-07-19
申请人： Telefonaktiebolaget L M Ericsson (publ)
发明人： András Császár , Balázs Peter Gerö , Gabor Sandor Enyedi
IPC分类号： H04L12/24 , H04L12/721 , H04L12/703 , H04L12/707 , H04L12/723
CPC分类号： H04L41/0668 , H04L45/12 , H04L45/22 , H04L45/28 , H04L45/50
摘要： A method is implemented by a network element or controller for determining a backup path for a fast reroute process to be utilized in response to a network event invalidating a primary path to a destination node. The method identifies at least one intermediate node that has a backup loop free alternative (LFA) path to a destination node in a network where no path meeting LFA conditions can be found for a point of local repair (PLR).
摘要翻译：网络元件或控制器实现一种方法，用于确定用于响应于使到达目的地节点的主要路径无效的网络事件而被利用的快速重路由进程的备份路径。该方法识别至少一个中间节点，该中间节点具有到网络中的目的地节点的备用无循环替代（LFA）路径，其中无法为局部修复（PLR）点找到满足LFA条件的路径。

86. 发明授权

US09424620B2 Identification of GPU phase to determine GPU scalability during runtime 有权
标题翻译：识别GPU阶段以确定运行时期间的GPU可扩展性
公开(公告)号：US09424620B2
公开(公告)日：2016-08-23
申请号：US13730908
申请日：2012-12-29
申请人： Intel Corporation
发明人： Idan Mondjak , Supratik Majumder , Eyal Yaacoby
IPC分类号： G06T1/20 , G06F1/32 , G09G5/36
CPC分类号： G06T1/20 , G06F1/3206 , G06F1/324 , G06F1/325 , G09G5/363 , G09G2330/021 , G09G2360/08 , G09G2360/121 , Y02D10/126
摘要： A method performed by a processor is described. The method may include identifying a graphics processing unit (GPU) phase of a frame, using said identified GPU phase to obtain frequency scalability information for said identified GPU phase, and determining whether to change a frequency at which a GPU is to draw said frame within said phase based on said frequency scalability information.
摘要翻译：描述由处理器执行的方法。该方法可以包括使用所识别的GPU相位来识别帧的图形处理单元（GPU）相位，以获得用于所述所识别的GPU相位的频率可伸缩性信息，以及确定是否改变GPU在其中绘制所述帧的频率所述相位基于所述频率可伸缩性信息。

87. 发明授权

US09378182B2 Vector move instruction controlled by read and write masks 有权
标题翻译：矢量移动指令由读写掩码控制
公开(公告)号：US09378182B2
公开(公告)日：2016-06-28
申请号：US13630118
申请日：2012-09-28
申请人： Intel Corporation
发明人： Mikhail Plotnikov , Andrey Naraikin , Christopher Hughes
IPC分类号： G06F15/00 , G06F15/76 , G06F15/80 , G06F9/38
CPC分类号： G06F15/8084 , G06F9/3885
摘要： A processor executes a vector move instruction to move data elements from a second vector register to a first vector register under the control of a first mask register and a second mask register. A register file within the processor includes the first vector register, the second vector register, the first mask register and the second mask register. In response to the vector move instruction, execution circuitry in the processor is to replace a given number of target data elements in the first vector register with the given number of source data elements in the second vector register. Each source data element corresponds to a mask bit in the second mask register having a second bit value, and wherein each target data element corresponds to a mask bit in the first mask register having a first bit value.
摘要翻译：处理器执行向量移动指令，以在第一屏蔽寄存器和第二屏蔽寄存器的控制下将数据元素从第二向量寄存器移动到第一向量寄存器。处理器内的寄存器文件包括第一向量寄存器，第二向量寄存器，第一掩码寄存器和第二掩码寄存器。响应于向量移动指令，处理器中的执行电路是用第二向量寄存器中的给定数量的源数据元素替换第一向量寄存器中给定数量的目标数据元素。每个源数据元素对应于具有第二位值的第二掩码寄存器中的掩码位，并且其中每个目标数据元素对应于具有第一位值的第一掩码寄存器中的掩码位。

88. 发明授权

US09300568B2 Procedure to add alternate paths for IS-IS default route 有权
标题翻译：为IS-IS默认路由添加备用路径的步骤
公开(公告)号：US09300568B2
公开(公告)日：2016-03-29
申请号：US14222243
申请日：2014-03-21
申请人： Telefonaktiebolaget L M Ericsson (publ)
发明人： Uma S. Chunduri , Vasant S. Patil , Wenhu Lu
IPC分类号： H04L12/54 , H04L12/733 , H04L12/707 , H04L12/715 , H04L12/721 , H04L12/705
CPC分类号： H04L45/122 , H04L45/04 , H04L45/12 , H04L45/18 , H04L45/22
摘要： A method is implemented by a network device to determine loop free alternatives (LFA) for each next hop in a default route to border nodes of a level 1 intermediate system-intermediate system (IS-IS) area of the network device. The method selects a next next-hop for the default route and looks up a corresponding border node for the selected next-hop in a local routing information base (RIB). A next next-hop of the corresponding border node is selected. A check is made whether the selected next-hop of the corresponding border node is the same as selected next-hop of default route. Then an LFA of the selected next-hop of the corresponding border node is assigned as LFA of the selected next-hop of the default route.
摘要翻译：网络设备实现一种方法，用于确定到网络设备的级别1中间系统 - 中间系统（IS-IS）区域的边界节点的默认路由中的每个下一跳的无循环替代（LFA）。该方法为默认路由选择下一个下一跳，并在本地路由信息库（RIB）中查找所选下一跳的相应边界节点。选择相应边界节点的下一个下一跳。检查相应边界节点的选定下一跳是否与默认路由选择的下一跳相同。然后将相应边界节点的所选下一跳的LFA分配为默认路由的所选下一跳的LFA。

89. 发明授权

US09246847B2 Extending the reach and effectiveness of header compression in access networks using SDN 有权
标题翻译：使用SDN扩展接入网络中头文件压缩的范围和有效性
公开(公告)号：US09246847B2
公开(公告)日：2016-01-26
申请号：US13717428
申请日：2012-12-17
申请人： TELEFONAKTIEBOLAGET L M ERICSSON (PUBL)
发明人： Ramesh Mishra , Ravi Manghirmalani , Ramesh Subrahmaniam
IPC分类号： H04L12/28 , H04L12/935 , H04L29/06 , H04L12/741 , H04L12/24 , H04L12/721
CPC分类号： H04L49/3009 , H04L41/0803 , H04L45/38 , H04L45/74 , H04L69/04 , H04L69/22
摘要： A method is executed by a controller in a software defined network to conserve bandwidth over the software defined networking (SDN) network by compressing Internet protocol (IP) headers of data packets traversing the SDN network. The IP headers of the data packets remain compressed as the data packets traverse the SDN network. The ingress switch is an entry point for the data packets as the data packets traverse the SDN network. The egress switch is an exit point for the data packets as the data packets traverse the SDN network. The method includes configuring a flow table of the ingress switch to forward the data packets to a header compressor module in the ingress switch, configuring the ingress switch to instantiate the header compressor module, and configuring a group table of the ingress switch to manage forwarding of the data packets toward the egress switch.
摘要翻译：一种由软件定义的网络中的控制器执行的方法，通过压缩穿过SDN网络的数据分组的因特网协议（IP）报头来通过软件定义的网络（SDN）网络来节省带宽。随着数据包穿越SDN网络，数据包的IP头部保持压缩。入口交换机是数据包穿越SDN网络时数据包的入口点。出口交换机是数据包穿越SDN网络时数据包的出口点。该方法包括配置入口交换机的流表，将数据包转发到入口交换机的报头压缩模块，配置入口交换机实例化报头压缩模块，配置入口交换机的组表，管理转发数据包朝向出口交换机。

90. 发明授权

US09191290B2 Methods and devices for monitoring a data path 有权
标题翻译：用于监视数据路径的方法和设备
公开(公告)号：US09191290B2
公开(公告)日：2015-11-17
申请号：US14128505
申请日：2012-06-19
申请人： Zhemin Ding , Panagiotis Saltsidis
发明人： Zhemin Ding , Panagiotis Saltsidis
IPC分类号： H04L12/26
CPC分类号： H04L43/062 , H04L43/026 , H04L43/0811 , H04L43/10
摘要： The present invention relates to methods and devices for monitoring a data path extending from an originating node to a terminating node in a network. In a first aspect of the present invention, the method comprises the step of submitting, to the originating node, a request to monitor at least one network status parameter associated with a particular data flow transported on the data path. Further, the method comprises the step of submitting, to all nodes in the data path, a data flow identifier indicating the particular data flow being one out of a plurality of data flows that can be transported on the data path. Moreover, the method comprises the step of receiving, from at least one of the nodes in the data path, a response message comprising the requested at least one network status parameter.
摘要翻译：本发明涉及用于监控从始发节点延伸到网络中的终止节点的数据路径的方法和设备。在本发明的第一方面中，所述方法包括以下步骤：向始发节点提交一个请求，以监视与数据路径上传输的特定数据流相关联的至少一个网络状态参数。此外，该方法包括向数据路径中的所有节点提交指示可以在数据路径上传输的多个数据流中的一个的特定数据流的数据流标识符的步骤。此外，该方法包括从数据路径中的至少一个节点接收包括所请求的至少一个网络状态参数的响应消息的步骤。

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