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81. 发明授权

US09262170B2 Out-of-order checkpoint reclamation in a checkpoint processing and recovery core microarchitecture 有权
标题翻译：检查点处理和恢复核心微架构中的无序检查点回收
公开(公告)号：US09262170B2
公开(公告)日：2016-02-16
申请号：US13558750
申请日：2012-07-26
申请人： Anil Krishna , Ganesh Balakrishnan , Gordon B. Bell
发明人： Anil Krishna , Ganesh Balakrishnan , Gordon B. Bell
IPC分类号： G06F9/00 , G06F9/44 , G06F9/38 , G06F11/14
CPC分类号： G06F9/3836 , G06F9/3859 , G06F9/3863 , G06F11/1407
摘要： Reclaiming checkpoints in a system in an order that differs from the order when the checkpoints are created. Reclaiming the checkpoints includes: creating one or more checkpoints, each of which having an initial state using system resources and holding the checkpoints state; identifying the completion of all the instructions associated with the checkpoint; reassigning all the instructions associated with the identified checkpoint to an immediately preceding checkpoint; and freeing the resources associated with the identified checkpoint. The checkpoint is created when the instruction that is checked is a conditional branch having a direction that cannot be predicted with a predetermined confidence level.
摘要翻译：以不同于创建检查点的顺序的顺序回收系统中的检查点。回收检查点包括：创建一个或多个检查点，每个检查点具有使用系统资源的初始状态并保持检查点状态; 确定与检查点相关联的所有指令的完成; 将与所识别的检查点相关联的所有指令重新分配给紧接在前的检查点; 并释放与识别的检查点相关联的资源。当检查的指令是具有不能以预定置信水平预测的方向的条件分支时，创建检查点。

82. 发明授权

US09230989B2 Hybrid CMOS nanowire mesh device and FINFET device 有权
标题翻译：混合CMOS纳米线网格器件和FINFET器件
公开(公告)号：US09230989B2
公开(公告)日：2016-01-05
申请号：US14194762
申请日：2014-03-02
申请人： International Business Machines Corporation
发明人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L29/66 , H01L27/12 , H01L21/28 , B82Y10/00 , B82Y40/00 , H01L21/84 , H01L29/06 , H01L29/423 , H01L29/78 , H01L29/786
CPC分类号： H01L27/1203 , B82Y10/00 , B82Y40/00 , H01L21/28 , H01L21/845 , H01L27/1211 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66795 , H01L29/785 , H01L29/78696
摘要： A semiconductor hybrid structure on an SOI substrate. A first portion of the SOI substrate containing a nanowire mesh device and a second portion of the SOI substrate containing a FINFET device. The nanowire mesh device including stacked and spaced apart semiconductor nanowires located on the substrate, each semiconductor nanowire having two end segments in which one of the end segments is connected to a source region and the other end segment is connected to a drain region; and a gate region over at least a portion of the stacked and spaced apart semiconductor nanowires, wherein each source region and each drain region is self-aligned with the gate region. The FINFET device including spaced apart fins on a top semiconductor layer on the second portion of the substrate; and a gate region over at least a portion of the fins.
摘要翻译： SOI衬底上的半导体混合结构。包含纳米线网状器件的SOI衬底的第一部分和包含FINFET器件的SOI衬底的第二部分。纳米线网状器件包括位于衬底上的层叠和间隔开的半导体纳米线，每个半导体纳米线具有两个端部段，其中一个端部段连接到源极区域，另一个端部段连接到漏极区域; 以及在所述堆叠并间隔开的半导体纳米线的至少一部分上的栅极区域，其中每个源极区域和每个漏极区域与栅极区域自对准。 FINFET器件包括在衬底的第二部分上的顶部半导体层上的间隔开的翅片; 以及在所述鳍片的至少一部分上方的栅极区域。

83. 发明授权

US09170296B2 Semiconductor device defect monitoring using a plurality of temperature sensing devices in an adjacent semiconductor device 有权
标题翻译：在相邻半导体器件中使用多个温度感测器件的半导体器件缺陷监视
公开(公告)号：US09170296B2
公开(公告)日：2015-10-27
申请号：US13960029
申请日：2013-08-06
申请人： International Business Machines Corporation
发明人： Kelly Malone , Brian L. Walsh
IPC分类号： G01R31/02 , G01R31/28 , G01R31/303
CPC分类号： G01R31/2875 , G01R31/303
摘要： An arrangement of semiconductor devices to monitor semiconductor defects. There is a first semiconductor device arranged in proximity to a second semiconductor device, the second semiconductor device having a plurality of temperature sensing devices at locations in the second semiconductor device; a plurality of through silicon vias extending between the first semiconductor device and the second semiconductor device to electrically connect the first semiconductor device to the second semiconductor device; and a testing program to cause the plurality of temperature sensing devices in the second semiconductor device to sense the temperature at a plurality of corresponding locations in the first semiconductor device such that a predetermined rise in temperature at one location of the plurality of temperature sensing devices in the second semiconductor device is indicative of a defect in the corresponding location in the first semiconductor device. Methods of monitoring defects are also disclosed.
摘要翻译：用于监测半导体缺陷的半导体器件的布置。存在布置在第二半导体器件附近的第一半导体器件，第二半导体器件在第二半导体器件中的位置处具有多个温度感测器件; 在第一半导体器件和第二半导体器件之间延伸的多个通硅通孔，以将第一半导体器件电连接到第二半导体器件; 以及测试程序，以使第二半导体器件中的多个温度感测装置感测第一半导体器件中的多个对应位置处的温度，使得多个温度感测装置的一个位置处的预定温度升高在第二半导体器件指示第一半导体器件中相应位置的缺陷。还公开了监测缺陷的方法。

84. 发明授权

US09052971B2 Scalable event-driven system 有权
标题翻译：可扩展的事件驱动系统
公开(公告)号：US09052971B2
公开(公告)日：2015-06-09
申请号：US13548158
申请日：2012-07-12
申请人： Joachin H. Frank , Ming Li , Liangzhao Zeng
发明人： Joachin H. Frank , Ming Li , Liangzhao Zeng
IPC分类号： G06F3/00 , G06F9/44 , G06F9/46 , G06F13/00 , G06F9/54
CPC分类号： G06F9/542 , G06F2209/546
摘要： Processing events in a distributed environment. There is provided an apparatus which includes a central queue for receiving events and tracking their progress through filtering, correlation, and update processing of stateful target objects, at least one filtering node, at least one correlation node and at least one update node. The central queue receives events in their order of arrival, each event having an entry in the central queue. Processing of events is divided into three pipelined stages in the order of filtering, correlating and updating. A result for each event of each of filtering the events, correlating the events and updating the target object is recorded in the central queue as part of the event's queue entry. The method may be performed by one or more computing devices. The exemplary embodiments detect and compensate for any erroneous results due to unsynchronized parallel processing, and guarantee an eventually correct outcome.
摘要翻译：在分布式环境中处理事件。提供了一种装置，其包括用于接收事件并通过对状态目标对象，至少一个过滤节点，至少一个相关节点和至少一个更新节点进行过滤，相关和更新处理来跟踪其进展的中心队列。中心队列以其到达顺序接收事件，每个事件在中心队列中具有条目。事件处理按照过滤，关联和更新的顺序分为三个流水线阶段。每个过滤事件，关联事件和更新目标对象的每个事件的结果作为事件队列条目的一部分记录在中央队列中。该方法可以由一个或多个计算设备执行。示例性实施例检测并补偿由于不同步并行处理引起的任何错误结果，并且保证最终正确的结果。

85. 发明授权

US09041082B2 Engineering multiple threshold voltages in an integrated circuit 有权
标题翻译：在集成电路中工程化多个阈值电压
公开(公告)号：US09041082B2
公开(公告)日：2015-05-26
申请号：US12899691
申请日：2010-10-07
申请人： Catherine Anne Dubourdieu , Martin Michael Frank , Vijay Narayanan
发明人： Catherine Anne Dubourdieu , Martin Michael Frank , Vijay Narayanan
IPC分类号： H01L21/02 , H01L21/28 , H01L21/8234 , H01L29/78
CPC分类号： H01L29/516 , H01L21/28291 , H01L21/823412 , H01L21/823462 , H01L27/088 , H01L29/78 , H01L29/7843
摘要： An integrated circuit and method for forming an integrated circuit. There are at least three field-effect transistors with at least two of the field-effect transistors having the same electrically insulating material which is ferroelectric when unstrained or is capable of being ferroelectric when strain is induced. It is optional for the third field-effect transistor to have an electrically insulating material which is ferroelectric when unstrained or is capable of being ferroelectric when strain is induced. The at least three field-effect transistors are strained to varying amounts so that each of the three field-effect transistors has a threshold voltage, Vt, which is different from the Vt of the two other field-effect transistors.
摘要翻译：一种用于形成集成电路的集成电路和方法。存在至少三个场效应晶体管，其中至少两个场效应晶体管具有相同的电绝缘材料，其在未应变时为铁电体，或者当诱发应变时能够为铁电体。对于第三场效应晶体管来说，具有电绝缘材料是可选的，其在未应变时为铁电体，或者当诱发应变时能够是铁电体。至少三个场效应晶体管被应变到不同的量，使得三个场效应晶体管中的每一个具有不同于另外两个场效应晶体管的Vt的阈值电压Vt。

86. 发明授权

US09020876B2 On-demand suggestion for vehicle driving 有权
标题翻译：汽车驾驶按需提示
公开(公告)号：US09020876B2
公开(公告)日：2015-04-28
申请号：US13490682
申请日：2012-06-07
申请人： Sarbajit K. Rakshit
发明人： Sarbajit K. Rakshit
IPC分类号： G06N5/02 , G01C21/34
CPC分类号： G01C21/3453 , B60W50/14 , B60W2550/402 , G01C21/3415 , G01C21/3461 , G06N5/02
摘要： A method of on-demand suggestion for vehicle driving which includes: providing a centralized vehicle driving knowledgebase containing previously-stored information pertaining to vehicle driving situations; responsive to a request for information pertaining to navigating a particular road situation, collecting current parameters pertaining to a current vehicle driving situation; providing the current parameters to the centralized vehicle driving knowledgebase; evaluating the current parameters with respect to the information previously stored in the centralized vehicle driving knowledgebase; and providing at least one suggestion to a vehicle for navigating the particular road situation. Also included is a computer program product for providing an on-demand suggestion for vehicle driving and a vehicle helping system.
摘要翻译：一种用于车辆驾驶的按需建议的方法，其包括：提供包含先前存储的关于车辆驾驶状况的信息的集中式车辆驾驶知识库; 响应于关于导航特定道路情况的信息的请求，收集与当前车辆驾驶状况有关的当前参数; 向中央车辆驾驶知识库提供当前参数; 评估与先前存储在集中式车辆驾驶知识库中的信息的当前参数; 并向车辆提供至少一个建议，用于导航特定的道路状况。还包括用于提供车辆驾驶的按需建议和车辆辅助系统的计算机程序产品。

87. 发明授权

US09006048B2 Fabricating photonics devices fully integrated into a CMOS manufacturing process 有权
标题翻译：制造完全集成到CMOS制造工艺中的光子器件
公开(公告)号：US09006048B2
公开(公告)日：2015-04-14
申请号：US14085748
申请日：2013-11-20
申请人： International Business Machines Corporation
发明人： Solomon Assefa , William M. J. Green , Yurii A. Vlasov , Min Yang
IPC分类号： H01L21/00 , H01L21/8238 , H01L21/762 , G02B6/136 , H01L31/0232 , H01L31/103 , H01L31/105 , H01L21/265
CPC分类号： H01L21/8238 , G02B6/136 , H01L21/26513 , H01L21/2658 , H01L21/76283 , H01L31/02327 , H01L31/103 , H01L31/105
摘要： Disclosed are process enhancements to fully integrate the processing of a photonics device into a CMOS manufacturing process flow. A CMOS wafer may be divided into different portions. One of the portions is for the CMOS devices and one or more other portions are for the photonics devices. The photonics devices include a ridged waveguide. One or more process steps may be performed simultaneously on the CMOS devices and the photonics devices.
摘要翻译：公开了将光子器件的处理完全集成到CMOS制造工艺流程中的过程增强。 CMOS晶片可以被分成不同的部分。其中一个部分用于CMOS器件，一个或多个其它部分用于光子器件。光子器件包括脊状波导。可以在CMOS器件和光子器件上同时执行一个或多个处理步骤。

88. 发明授权

US08950661B2 Realizing desktop metaphors on a computer 有权
标题翻译：在电脑上实现桌面隐喻
公开(公告)号：US08950661B2
公开(公告)日：2015-02-10
申请号：US13632260
申请日：2012-10-01
申请人： International Business Machines Corporation
发明人： Tomio Amano
IPC分类号： G06F17/00
CPC分类号： G06F1/1696
摘要： A desktop metaphor system. There is included a physical, non-virtual icon card corresponding to a certain computer application and a computer separate from the icon card. The computer includes a computer readable storage medium for storing computer applications, one of which is the certain computer application, and a computer processor. The computer processor includes an icon detection module to detect the approaching of the icon card to the computer and recognize the certain computer application corresponding to the icon card; an application context memory module for storing application context for an application running on the computer processor and for storing application context for the certain application corresponding to the icon card and stored in storage; and an event processing logic module for switching between the application, if any, currently running on the computer processor and the certain application corresponding to the icon card.
摘要翻译：桌面隐喻系统。包括对应于特定计算机应用的物理，非虚拟图标卡和与图标卡分开的计算机。计算机包括用于存储计算机应用的计算机可读存储介质，其中一个是特定计算机应用程序，以及计算机处理器。计算机处理器包括图标检测模块，用于检测图标卡到计算机的接近并识别对应于图标卡的某些计算机应用; 应用程序上下文存储器模块，用于存储在计算机处理器上运行的应用程序的应用程序上下文，并存储与图标卡对应的存储在存储器中的特定应用的应用程序上下文; 以及事件处理逻辑模块，用于在计算机处理器上当前运行的应用程序（如果有的话）和对应于图标卡的某个应用程序之间进行切换。

89. 发明授权

US08912056B2 Dual epitaxial integration for FinFETS 有权
标题翻译： FinFETS的双外延集成
公开(公告)号：US08912056B2
公开(公告)日：2014-12-16
申请号：US13860791
申请日：2013-04-11
申请人： International Business Machines Corporation
发明人： Veeraraghavan S. Basker , Effendi Leobandung , Xinhui Wang , Tenko Yamashita
IPC分类号： H01L21/84 , H01L21/331 , H01L21/337
CPC分类号： H01L21/845
摘要： A dual epitaxial integration process for FinFET devices. First and second pluralities of fins and gates are formed, with some of the fins and gates being for NFETs and some of the fins and gates being for PFETs. A first layer of a hard mask material selected from the group consisting of titanium nitride, tungsten nitride, tantalum nitride, amorphous carbon and titanium carbide is deposited over the NFETs and PFETs. The hard mask material is removed from one of the NFETs and PFETs and a first source and drain material is epitaxially deposited on the fins. A second layer of the hard mask material is deposited over the NFETs and PFETs. The first and second layers of the hard mask material are removed from the other of the NFETs and PFETs and a second source and drain material is deposited on the fins.
摘要翻译： FinFET器件的双外延集成工艺。形成第一和第二多个鳍和栅极，其中一些鳍和栅极用于NFET，并且一些鳍和栅极用于PFET。选自氮化钛，氮化钨，氮化钽，无定形碳和碳化钛的第一层硬掩模材料沉积在NFET和PFET上。从NFET和PFET中的一个去除硬掩模材料，并且第一源极和漏极材料外延地沉积在鳍片上。第二层硬掩模材料沉积在NFET和PFET上。硬掩模材料的第一和第二层从NFET和PFET中的另一个去除，并且第二源极和漏极材料沉积在鳍片上。

90. 发明授权

US08796747B2 Photonics device and CMOS device having a common gate 有权
标题翻译：具有公共栅极的光子器件和CMOS器件
公开(公告)号：US08796747B2
公开(公告)日：2014-08-05
申请号：US13736672
申请日：2013-01-08
申请人： International Business Machines Corporation
发明人： Solomon Assefa , William M. J. Green , Steven M. Shank , Yurii A. Vlasov
IPC分类号： H01L21/762
CPC分类号： H01L27/0922 , H01L21/28255 , H01L21/823437 , H01L21/84 , H01L27/0617 , H01L27/14 , H01L31/18 , H01L31/1808 , Y02E10/50
摘要： A semiconductor chip having a photonics device and a CMOS device which includes a photonics device portion and a CMOS device portion on a semiconductor chip; a metal or polysilicon gate on the CMOS device portion, the metal or polysilicon gate having a gate extension that extends toward the photonics device portion; a germanium gate on the photonics device portion such that the germanium gate is coplanar with the metal or polysilicon gate, the germanium gate having a gate extension that extends toward the CMOS device portion, the germanium gate extension and metal or polysilicon gate extension joined together to form a common gate; spacers formed on the germanium gate and the metal or polysilicon gate; and nitride encapsulation formed on the germanium gate. A method is also disclosed pertaining to fabricating the semiconductor chip.
摘要翻译：一种具有光子器件和CMOS器件的半导体芯片，其包括半导体芯片上的光子器件部分和CMOS器件部分; 在CMOS器件部分上的金属或多晶硅栅极，金属或多晶硅栅极具有朝向光子器件部分延伸的栅极延伸; 在光子器件部分上的锗栅极，使得锗栅极与金属或多晶硅栅极共面，锗栅极具有朝向CMOS器件部分延伸的栅极延伸，锗栅极延伸和金属或多晶硅栅极延伸部连接到一起形成共同门; 在锗栅极和金属或多晶硅栅极上形成的间隔物; 并且在锗栅上形成氮化物封装。还公开了一种制造半导体芯片的方法。

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