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    • 81. 发明授权
    • Electronic timepiece
    • 电子钟表
    • US4275463A
    • 1981-06-23
    • US58170
    • 1979-07-17
    • Takashi Ishida
    • Takashi Ishida
    • G04C9/08G04C9/00G04G9/08
    • G04G9/08G04C9/00
    • An electronic timepiece having a stepping motor which can be driven at a normal frequency and at a relatively faster correction frequency includes a manually actuable switch and circuitry responsive to two successive actuations of the switch within a first predetermined time period for effecting a change in the motor drive from the normal frequency to the correction frequency and responsive to a third actuation of the switch after a predetermined time period from said change, to return the motor drive to the normal frequency.
    • 具有可以以正常频率和相对较快校正频率驱动的步进电机的电子钟表包括手动致动开关和响应于在第一预定时间段内开关的两次连续致动的电路,以实现电动机的变化 从所述正常频率驱动到所述校正频率,并且响应于在从所述改变的预定时间段之后所述开关的第三次动作,以将所述马达驱动器返回到所述正常频率。
    • 83. 发明授权
    • Electronic timepiece
    • 电子钟表
    • US4262347A
    • 1981-04-14
    • US906559
    • 1978-05-16
    • Seiko SasakiKazuhiro Asano
    • Seiko SasakiKazuhiro Asano
    • G04D7/00G04G5/00G04G99/00G11C29/00G11C29/56G04C15/00
    • G04G99/006G04D7/002
    • An electronic timepiece including a ROM program memory for storing a program, a program counter for addressing the program memory, and a RAM data memory. An operating circuit including an arithmetic logic circuit operates on the data. The ROM program memory circuit stores a test program, and the program counter includes preset test means for addressing the test program stored in the ROM program circuit to operate the timepiece according to the test program. The program memory counter also includes jump inhibiting means for inhibiting execution of the operating program stored in the ROM program memory, in response to a jump address.
    • 一种包括用于存储程序的ROM程序存储器,用于寻址程序存储器的程序计数器和RAM数据存储器的电子表。 包括算术逻辑电路的操作电路对数据进行操作。 ROM程序存储电路存储测试程序,并且程序计数器包括用于寻址存储在ROM程序电路中的测试程序的预设测试装置,以根据测试程序操作该时计。 程序存储计数器还包括响应于跳转地址而禁止执行存储在ROM程序存储器中的操作程序的跳转禁止装置。
    • 84. 发明授权
    • Date driving mechanism of watch
    • 手表日期驱动机制
    • US4261047A
    • 1981-04-07
    • US49990
    • 1979-06-19
    • Hideyuki Nakao
    • Hideyuki Nakao
    • G04B19/253G04B19/24G04B19/20
    • G04B19/25353
    • The date driving mechanism of a watch comprises a date driving wheel having a partially teethed portion engaged with teeth of a calendar driving wheel which in turn drives a calendar display dial so as to advance the calendar display dial a given amount each rotation of the date driving wheel. A cam integral with the date driving wheel engages a pivotal control member so as to hold the control member against the calendar driving wheel normally to restrain movement of the date dial. The cam has a flat side so as to release the calendar driving wheel from restraint when being driven by the teethed portion of the date driving wheel, thereby relieving load on the date driving wheel. The control member has a resilient arm which yields to permit manual correction of the calendar display.
    • 手表的日期驱动机构包括日期驱动轮,该日期驱动轮具有与日历驱动轮的齿接合的部分开口部分,该日历驱动轮依次驱动日历显示拨盘,以使日历显示拨盘在日期驱动 轮。 与日期驱动轮一体的凸轮与枢转控制构件接合,以便将控制构件正常地抵靠在日历驱动轮上以限制日期拨盘的移动。 凸轮具有平坦的侧面,以便在由日期驱动轮的前端部分驱动时将日历驱动轮从限制释放,从而减轻日期驱动轮上的负载。 控制构件具有弹性臂,其产生以允许手动校正日历显示。
    • 85. 发明授权
    • Interlevel interface for series powered IIL or SITL
    • 串联电源IIL或SITL的接口
    • US4256984A
    • 1981-03-17
    • US913670
    • 1978-06-08
    • Masayuki Kojima
    • Masayuki Kojima
    • H01L27/02H01L27/04H03K19/091H03K19/092
    • H01L27/0225H03K19/091
    • In a Static Induction Transistor Logic (or an Integrated Injection Logic) semiconductor device having a lateral PNP transistor used as an injector and a longitudinal field effect transistor (or a longitudinal NPN transistor) used as a driving transistor, a collector of a transistor for a level-converter which converts a signal level from an upper layer or first logic level to a lower layer or second logic level is connected to a gate (or a base) of a driving transistor placed in the lower layer through a current limiting element integrated on the same chip to effectively use an injection current in a signal-level converting circuit used in a Static Induction Transistor Logic or in an Integrated Injection Logic which is constructed by using a laminated circuit construction.
    • 在具有用作注入器的横向PNP晶体管和用作驱动晶体管的纵向场效应晶体管(或纵向NPN晶体管)的静态感应晶体管逻辑(或集成注入逻辑)半导体器件中,用于 将来自上层或第一逻辑电平的信号电平转换为较低层或第二逻辑电平的电平转换器通过集成在其上的限流元件连接到位于下层中的驱动晶体管的栅极(或基极) 相同的芯片在静态感应晶体管逻辑中使用的信号电平转换电路中有效地使用注入电流,或者通过使用层叠电路结构构造的集成注入逻辑中。
    • 86. 发明授权
    • Thickness-width shear quartz crystal vibrator
    • 厚度剪切石英晶体振动器
    • US4234812A
    • 1980-11-18
    • US929027
    • 1978-07-28
    • Hirofumi Kawashima
    • Hirofumi Kawashima
    • H03H9/17H03H9/19H03H9/56H01L41/08H01L41/18
    • H03H9/02023H03H9/566
    • A thickness-width shear quartz crystal vibrator, having each vibrating mode (p, q, r) respectively being (1, 1, 1), in which "p" is the number of crests of a sine wave form of polarization directed along its electrical axis, "q" is the number of crests of a cosine waveform of polarization directed along its thickness and "r" is the number of crests of cosine waveform of polarization directed along its width perpendicular to the said electrical axis. The vibrator is cut out from a Y-plate of quartz crystal at the angle between 34 to 36 degrees turned around the X-axis thereof and is provided with plural opposite electrodes on the vertical surface or the surface parallel to the y-axis thereof. Therefore, the said quartz crystal vibrator has a low equivalent impedance and also has an excellent frequency-temperature characteristic.
    • 每个振动模式(p,q,r)的厚度 - 宽度剪切石英晶体振动器分别为(1,1,1),其中“p”是沿着它的正弦波形极化的波峰数 电轴,“q”是沿着其厚度指向的偏振的余弦波形的波峰数,“r”是沿其垂直于所述电轴的宽度指向的偏振的余弦波形的波峰数。 振动器从石英晶体的Y板切割成围绕其X轴的34至36度之间的角度,并且在垂直表面或平行于其y轴的表面上设置有多个相对的电极。 因此,所述石英晶体振子具有低等效阻抗,并且也具有优异的频率 - 温度特性。
    • 87. 发明授权
    • Voltage regulated electronic timepiece
    • 电压调节电子表
    • US4217540A
    • 1980-08-12
    • US918594
    • 1978-06-23
    • Nobuo Shimotsuma
    • Nobuo Shimotsuma
    • G04C10/00G04G19/06G05F3/20G05F3/08
    • G05F3/20G04G19/06
    • A voltage regulating circuit for supplying a regulated voltage to an electronic circuit of an electronic timepiece. The voltage regulating circuit is comprised of an N-MOS and a P-MOS transistor pair connected in series with drains and gates connected together at a common junction, and a constant current source for providing a constant current through the transistor pair for developing the regulated voltage thereacross. The constant current source is comprised of a third MOS transistor connected in series with the transistor pair, and a biasing circuit for biasing the third MOS transistor to provide a constant current through the transistor pair. The voltage regulating circuit and the electronic circuit of the electronic timepiece are both integrated circuits formed on a common integrated circuit chip.
    • 一种用于向电子钟表的电子电路提供调节电压的电压调节电路。 电压调节电路由与公共接点连接在一起的漏极和栅极串联连接的N-MOS和P-MOS晶体管对组成,以及恒流源,用于通过晶体管对提供恒定电流,用于显影调节 电压。 恒流源包括与晶体管对串联的第三MOS晶体管,以及用于偏置第三MOS晶体管以提供通过晶体管对的恒定电流的偏置电路。 电子计时器的电压调节电路和电子电路都是形成在公共集成电路芯片上的集成电路。