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    • 83. 发明授权
    • Adapter apparatus and method for transmitting electronic data
    • 用于发送电子数据的适配器装置和方法
    • US6146153A
    • 2000-11-14
    • US265000
    • 1999-03-03
    • Amir KoradiaPhilip A. RavlinJohn J. Connell
    • Amir KoradiaPhilip A. RavlinJohn J. Connell
    • H01R12/55H01R31/02H01R12/00
    • H01R12/716H01R31/02
    • An adapter apparatus for transmitting electronic data includes a circuit board having a first side and a second side. At least two male connectors are positioned adjacent to the first side of the circuit board. Each of the at least two male connectors includes a plurality of transmit-receive pairs of pins. Each of the plurality of transmit-receive pairs of pins includes a pin for transmitting data and a pin for receiving data. A first pin header is positioned adjacent the second side of the circuit board. The first pin header includes a plurality of pins for receiving data. A second pin header is positioned adjacent the second side of the circuit board. The second pin header includes a plurality of pins for transmitting data. The plurality of pins for receiving data and the plurality of pins for transmitting data are operatively connected to the plurality of transmit-receive pairs of pins.
    • 用于发送电子数据的适配器装置包括具有第一侧和第二侧的电路板。 至少两个阳连接器邻近电路板的第一侧定位。 所述至少两个公连接器中的每一个包括多个发送 - 接收对引脚对。 多个发送 - 接收对引脚中的每一个包括用于发送数据的引脚和用于接收数据的引脚。 第一引脚头位于电路板的第二侧附近。 第一引脚接头包括用于接收数据的多个引脚。 第二针头位于电路板的第二侧附近。 第二针头包括用于传送数据的多个针脚。 用于接收数据的多个引脚和用于发送数据的多个引脚可操作地连接到多个发送 - 接收对引脚对。
    • 84. 发明授权
    • Method and system for modification of fax data rate over wireless
channels
    • 通过无线信道修改传真数据速率的方法和系统
    • US6144464A
    • 2000-11-07
    • US927693
    • 1997-09-11
    • Scott W. RuppJohn WheelerBrady Brown
    • Scott W. RuppJohn WheelerBrady Brown
    • H04B7/26H04L1/00H04L1/18H04N1/00H04N1/333H04Q7/32H04N1/32
    • H04N1/33361H04B7/2659H04L1/0002H04N1/00281H04N1/3333H04L1/18H04N2201/3335
    • A method and apparatus for improving the successful transmission of facsimile data over a wireless communication channel is provided comprising a facsimile machine, a wireless transceiver and a connector interfacing therebetween. The facsimile machine detects an interface with the wireless transceiver and notifies the facsimile machine of a wireless communication channel through which facsimile data will traverse. The facsimile machine, in conjunction with the wireless transceiver, establishes a wireless communication channel according to an initial data transfer rate corresponding with the capability of the wireless transceiver or known communication channel conditions. The facsimile machine then exchanges facsimile data over the wireless communication channel and a receiving facsimile machine evaluates the facsimile data to detect errors injected through the wireless communication channel. When such errors are detected, the facsimile machine may institute retransmission of the previous facsimile data relying upon an anticipated improved condition of the wireless communication channel. When the conditions of this wireless communication channel have not improved, the facsimile machine renegotiates a data transfer rate more conducive with the present capability of the wireless communication channel. A facsimile machine further determines when the wireless transceiver is removed and reverts back to traditional wired communication channel data rates.
    • 提供了一种用于通过无线通信信道改善传真数据的成功传输的方法和装置,其包括传真机,无线收发机以及在它们之间的连接器。 传真机检测与无线收发器的接口,并向传真机通知传真数据将穿过的无线通信信道。 传真机与无线收发器结合,根据与无线收发机的能力对应的初始数据传输速率或已知的通信信道条件建立无线通信信道。 然后,传真机通过无线通信信道交换传真数据,接收传真机对传真数据进行评估,以检测通过无线通信信道注入的错误。 当检测到这样的错误时,传真机可以依赖于无线通信信道的预期改进状况来重传先前的传真数据。 当该无线通信信道的条件没有改善时,传真机重新协商更有利于无线通信信道当前能力的数据传输速率。 传真机进一步确定无线收发器何时被去除并且回复到传统的有线通信信道数据速率。
    • 85. 发明授权
    • Coherence mechanism for distributed address cache in a network switch
    • 网络交换机中分布式地址缓存的一致性机制
    • US6141344A
    • 2000-10-31
    • US44293
    • 1998-03-19
    • Kenneth J. DeLong
    • Kenneth J. DeLong
    • H04L12/70H04L12/747H04L12/933H04L12/935H04L12/50
    • H04L49/101H04L45/742H04L49/3009H04L2012/5681
    • In a network switch with a distributed address cache, events that update a cache segment are serialized and distributed and acted upon by all the cache segments to maintain consistency among the segments. The segments are individually associated with Input/Output Application Specific Integrated Circuits ("I/O ASICs") interconnected via an event sharing bus used for transmission of cache update messages. Messages are ordered by arbitrating for the shared bus and enforcing that an I/O ASIC does not update its local cache segment until a cache update message is broadcast on the event bus. Each I/O ASIC asserts a busy signal while executing a cache update message to prevent an arbiter from granting the event bus to allow transmission of a subsequent update message; thereby synchronizing all update messages and minimizing storage on each I/O ASIC for update messages. A weakly coherent mechanism predicated on the observation that address learning operations and address aging operations are self correcting is employed which permits cache update messages to be flushed when cache line conflicts are detected.
    • 在具有分布式地址高速缓存的网络交换机中,更新高速缓存段的事件被所有高速缓存段序列化并分布和执行,以保持段之间的一致性。 这些段与通过用于传输缓存更新消息的事件共享总线互连的输入/输出专用集成电路(“I / O ASIC”)单独地相关联。 通过对共享总线进行仲裁来排序消息,并强制I / O ASIC不更新其本地高速缓存段,直到在事件总线上广播高速缓存更新消息。 每个I / O ASIC在执行高速缓存更新消息时断言忙信号,以防止仲裁器授予事件总线以允许后续更新消息的传输; 从而同步所有更新消息并最小化每个I / O ASIC上的存储以获得更新消息。 采用基于对地址学习操作和地址老化操作进行自校正的观察结果的弱相干机制,当检测到高速缓存行冲突时允许高速缓存更新消息被刷新。
    • 86. 发明授权
    • Media jack with switch for LAN and modem connection
    • 介质插孔,带有LAN和调制解调器连接的开关
    • US6139342A
    • 2000-10-31
    • US183830
    • 1998-10-30
    • Curtis D. Thompson
    • Curtis D. Thompson
    • H01R13/703H01R24/00H04L12/56H01R29/00
    • H01R13/703H01R24/62H04L49/351Y10S439/955
    • A media jack is provided having an aperture configured to receive a first media plug and a second media plug each of different configuration. A plurality of discrete contact wires extend from the housing into the aperture. Positioned on the side of the housing is a switch arm having a first contact and second contact positioned at the opposing sides thereof. The switch arm is operable between a first position and a second position. In the first position, the switch arm biases in electrical contact with the first contact such that a head of the switch arm is disposed within the aperture of the media plug. In this position, a discrete contact wire communicates with a first electrical pathway including the first contact and switch arm. In the second position, switch arm is manually pushed backwards so that the switch arm is in electrical communication with the second contact. In this configuration, the discrete contact wire is in communication with a second electrical pathway including that switch arm and second contact.
    • 提供一种介质插座,其具有被配置为接收每个不同配置的第一介质插头和第二介质插头的孔。 多个离散接触线从壳体延伸到孔中。 位于壳体侧面的是具有位于其相对侧的第一接触件和第二接触件的开关臂。 开关臂可在第一位置和第二位置之间操作。 在第一位置,开关臂偏压与第一接触件电接触,使得开关臂的头部设置在介质塞的孔内。 在该位置,分立的接触线与包括第一接触和开关臂的第一电路连通。 在第二位置,手动向后推动开关臂,使得开关臂与第二接触件电连通。 在该配置中,分立接触导线与包括该开关臂和第二接触件的第二电路连通。
    • 87. 发明授权
    • Apparatus and method for mounting a transition connector and a telephone
connector back-to-back on a circuit board
    • 将过渡连接器和电话连接器背对背地安装在电路板上的装置和方法
    • US6129557A
    • 2000-10-10
    • US206575
    • 1998-12-07
    • Marion BlaszczykDane L. GreivesJohn J. ConnellAmir Koradia
    • Marion BlaszczykDane L. GreivesJohn J. ConnellAmir Koradia
    • H01R12/00H01R12/71
    • H01R12/712H01R12/707H01R12/737
    • An apparatus for mounting a transition connector and a telephone connector back-to-back on circuit board is provided. A circuit board is adapted for placement in an electronic chassis and includes a front side and a back side. A transition connector is operatively connected to the front side of the circuit board. The transition connector includes a plurality of spaced apart pins arranged in a first row and a second opposing row. The first row is spaced apart from the second row a first distance. A telephone connector is operatively connected to the back side of the circuit board opposite the transition connector. The telephone connector includes a plurality of spaced apart pins arranged in a first line and a second opposing line. The first line is spaced apart from the second line a second distance. The first distance is greater than the second distance. The first and second lines are positioned between the first and second rows. The pins of the first row are operatively connected to the pins of the first line, and the pins of the second row are operatively connected to the pins of the second line.
    • 提供一种用于在电路板上背对背地安装过渡连接器和电话连接器的装置。 电路板适于放置在电子底盘中,并且包括前侧和后侧。 过渡连接器可操作地连接到电路板的前侧。 过渡连接器包括布置在第一行和第二相对行中的多个间隔开的销。 第一排与第二排隔开第一距离。 电话连接器可操作地连接到与过渡连接器相对的电路板的背面。 电话连接器包括布置在第一线和第二相对线中的多个间隔开的销。 第一行与第二行间隔第二距离。 第一距离大于第二距离。 第一和第二行位于第一行和第二行之间。 第一行的销可操作地连接到第一行的销,并且第二行的销可操作地连接到第二行的销。
    • 88. 发明授权
    • Self-initiated system event using network resources
    • 使用网络资源的自发系统事件
    • US6128658A
    • 2000-10-03
    • US177706
    • 1998-10-22
    • David Peter McLean
    • David Peter McLean
    • H04L29/06H04L29/08G06F15/173G06F15/16
    • H04L67/36H04L29/06H04L67/22H04L69/329
    • A method for testing the remote wake-up function of a computer system, wherein the computer system includes a circuit for performing the wake-up function in response to a wake-up packet. First, the computer system sends over the network a broadcast message that includes the network address of the computer system. The broadcast message requests one or more directed responses from the computer systems on the network, where the directed responses represent directed test wake-up packets. Subsequently, the computer system receives the directed test wake-up packets and generates a list of computer systems, and the network address associated with each of the computer systems, that responded to the broadcast message. The computer system then sends directed messages to a subset of the list of computer systems that responded to the broadcast message, where each of the directed messages requests that the subset of computer systems send a delayed test wake-up packet. Next, the computer system powers down, and then wakes up in response to the aforementioned circuit receiving one of the delayed test wake-up packets. In this manner, the present invention provides a method for initiating and executing a self-test of the remote wake-up function.
    • 一种用于测试计算机系统的远程唤醒功能的方法,其中所述计算机系统包括用于响应于唤醒分组来执行唤醒功能的电路。 首先,计算机系统通过网络发送包括计算机系统的网络地址的广播消息。 广播消息请求来自网络上的计算机系统的一个或多个定向响应,其中定向响应表示定向的测试唤醒分组。 随后,计算机系统接收定向测试唤醒分组,并产生响应于广播消息的计算机系统列表和与每个计算机系统相关联的网络地址。 计算机系统然后将定向消息发送到响应于广播消息的计算机系统列表的子集,其中每个定向消息请求计算机系统的子集发送延迟的测试唤醒分组。 接下来,计算机系统断电,然后响应于上述电路接收延迟测试唤醒分组之一而唤醒。 以这种方式,本发明提供了一种启动和执行远程唤醒功能的自检的方法。
    • 89. 发明授权
    • Method and system for interfacing parallelly interfaced devices through
a serial bus
    • 用于通过串行总线连接并行连接的设备的方法和系统
    • US6128311A
    • 2000-10-03
    • US31103
    • 1998-02-26
    • Spiro PoulisDavid M. Arnesen
    • Spiro PoulisDavid M. Arnesen
    • G06F13/42H04L12/66
    • G06F13/4286
    • A method and apparatus for interconnecting via a serial bus a master processor and a co-processor having directly interfaceable parallel interfaces thereby accommodating the remote location of the co-processor from the master processor. The master processor interfaces with a serial bus interface for converting the parallel interface of the master processor into a serial interface forming a serial bus including a serial data out signal, a serial data in signal, a serial clock signal and a frame sync signal. The serial bus interfaces with the remote module having the co-processor located therein. The serial bus interfaces directly with an interface controller for converting the serial information back to a parallel format compatable with the requirements of the co-processor's parallel interface. The interface controller is further capable of generating control signals such as resets and general purpose outputs when directed by the master processor and reading status of the co-processor when also directed by the master processor. Testing functionality is also included for specific incorporation of an ISDN-specific I/O interface device functioning as the co-processor.
    • 一种用于经由串行总线互连主处理器和具有直接可接口的并行接口的协处理器的方法和装置,从而从主处理器容纳协处理器的远程位置。 主处理器与串行总线接口连接,用于将主处理器的并行接口转换成串行接口,形成串行数据输出信号,信号串行数据,串行时钟信号和帧同步信号的串行总线。 串行总线与位于其中的协处理器的远程模块接口。 串行总线直接与接口控制器接口,用于将串行信息转换为与协处理器并行接口的要求相兼容的并行格式。 当由主处理器指导时,接口控制器还能够产生诸如复位和通用输出的控制信号,并且当主处理器也指示时,该协处理器的读取状态。 还包括测试功能,用于特定并入用作协处理器的ISDN专用I / O接口设备。
    • 90. 发明授权
    • System and method for selecting a loudest speaker by comparing average
frame gains
    • 通过比较平均帧增益来选择最大扬声器的系统和方法
    • US06125343A
    • 2000-09-26
    • US865399
    • 1997-05-29
    • Guido M. Schuster
    • Guido M. Schuster
    • G10L21/02G06F7/08
    • G10L21/028
    • An improved system for identifying the loudest speech signal in a G.723.1 based audio teleconferencing link is disclosed. The system selects the loudest of several analog audio signals by directly analyzing the encoded G.723.1 bit streams representing those signals, rather than by decoding the encoded speech signal in the G.723.1 bit streams and then re-encoding the signal as a selected output bit stream. The system uses the excitation gain parameters encoded in G.723.1 frames to approximate frame gains for respective bit streams and then estimates a short term speech energy for each bit stream by averaging the approximate frame gains over time. The system then compares the estimated speech energy levels and outputs to each conference participant the signal with the highest estimated speech energy as the next portion of an output signal.
    • 公开了一种用于识别基于G.723.1的音频电话会议链路中最响亮的语音信号的改进系统。 系统通过直接分析代表这些信号的编码的G.723.1比特流而不是通过对G.723.1比特流中的编码语音信号进行解码,然后将该信号重新编码为选择的输出,来选择最大的几个模拟音频信号 位流。 该系统使用G.723.1帧中编码的激励增益参数来近似各个比特流的帧增益,然后通过对随时间推移的近似帧增益进行平均来估计每个比特流的短期语音能量。 然后,系统将估计的语音能级和输出与具有最高估计语音能量的信号作为输出信号的下一部分比较。