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71. 发明授权

US09058971B2 Electro-optical module 有权
标题翻译：电光模块
公开(公告)号：US09058971B2
公开(公告)日：2015-06-16
申请号：US13905703
申请日：2013-05-30
申请人： Siliconware Precision Industries Co., Ltd.
发明人： Chih-Yuan Shih , Shih-Liang Peng , Jung-Pin Huang , Chin-Yu Ku , Hsien-Wen Chen
IPC分类号： H01L27/15 , H01L29/26 , H01L31/12 , H01L33/00 , H01L25/00 , H01S5/022 , H01S5/024 , H01S5/062 , H01S5/42
CPC分类号： H01L25/00 , H01L2224/48091 , H01S5/02252 , H01S5/0226 , H01S5/02276 , H01S5/02288 , H01S5/02469 , H01S5/06226 , H01S5/423 , H01L2924/00014
摘要： An electro-optical module is provided, which includes: a substrate having a first surface with a groove and an opposite second surface; a plurality of support members disposed on the first surface of the substrate; at least an electro-optical element having opposite active and non-active surfaces and disposed in the groove of the substrate via the non-active surface thereof; an interposer disposed on the first surface of the substrate and the electro-optical element for electrically connecting the electro-optical element to the substrate, wherein the interposer has a through hole corresponding in position to the active surface of the electro-optical element; and a transparent plate disposed over the first surface of the substrate and the interposer through the support members and having a lens portion corresponding in position to the through hole of the interposer, thereby reducing signal losses, improving alignment precision, and achieving preferred thermal dissipation and EMI shielding effects.
摘要翻译：提供了一种电光模块，其包括：具有第一表面和第二表面的基板; 设置在所述基板的第一表面上的多个支撑构件; 至少一个电光元件具有相对的有源和非有源表面，并经由其非有效表面设置在衬底的沟槽中; 设置在基板的第一表面上的插入器和用于将电光元件电连接到基板的电光元件，其中插入器具有与电光元件的有源表面相对应的通孔; 以及设置在基板的第一表面上的透明板和穿过支撑构件的中介层，并且具有与插入件的通孔对应的透镜部分，从而减少信号损失，提高对准精度，并实现优选的散热和 EMI屏蔽效果。

72. 发明授权

US09054205B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09054205B2
公开(公告)日：2015-06-09
申请号：US14064294
申请日：2013-10-28
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Shunpei Yamazaki , Yusuke Nonaka , Takatsugu Omata , Tatsuya Honda , Akiharu Miyanaga , Hiroki Ohara
IPC分类号： H01L29/12 , H01L29/786 , H01L29/417 , H01L29/45 , H01L29/49 , H01L29/26 , H01L27/12
CPC分类号： H01L29/78693 , H01L27/1225 , H01L27/124 , H01L29/263 , H01L29/41733 , H01L29/45 , H01L29/4908 , H01L29/78618 , H01L29/78621 , H01L29/7869
摘要： A semiconductor device having a novel structure or a method for manufacturing the semiconductor device is provided. For example, the reliability of a transistor which is driven at high voltage or large current is improved. For improvement of the reliability of the transistor, a buffer layer is provided between a drain electrode layer (or a source electrode layer) and an oxide semiconductor layer such that the end portion of the buffer layer is beyond the side surface of the drain electrode layer (or the source electrode layer) when seen in a cross section, whereby the buffer layer can relieve the concentration of electric field. The buffer layer is a single layer or a stacked layer including a plurality of layers, and includes, for example, an In—Ga—Zn—O film containing nitrogen, an In—Sn—O film containing nitrogen, an In—Sn—O film containing SiOx, or the like.
摘要翻译：提供具有新颖结构的半导体器件或半导体器件的制造方法。例如，提高了以高电压或大电流驱动的晶体管的可靠性。为了提高晶体管的可靠性，在漏电极层（或源极电极层）和氧化物半导体层之间设置缓冲层，使得缓冲层的端部超出漏电极层的侧面（或源电极层），从而缓冲层能够缓和电场的集中。缓冲层是包含多个层的单层或层叠层，例如包含氮的In-Ga-Zn-O膜，含有氮的In-Sn-O膜，In-Sn-O系膜， O膜等。

73. 发明授权

US09024669B2 Storage element, storage device, and signal processing circuit 有权
标题翻译：存储元件，存储设备和信号处理电路
公开(公告)号：US09024669B2
公开(公告)日：2015-05-05
申请号：US14068217
申请日：2013-10-31
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Takuro Ohmaru , Masami Endo
IPC分类号： H03K3/356 , H01L27/108 , G11C11/24 , H01L29/26
CPC分类号： H01L27/1052 , G06F1/3275 , G11C11/24 , G11C14/0009 , G11C19/184 , H01L23/5226 , H01L27/0629 , H01L27/108 , H01L27/10805 , H01L27/10897 , H01L28/20 , H01L28/40 , H01L29/24 , H01L29/26 , H01L29/7869 , Y02D10/13 , Y02D10/14
摘要： A signal processing circuit whose power consumption can be suppressed is provided. In a period during which a power supply voltage is not supplied to a storage element, data stored in a first storage circuit corresponding to a nonvolatile memory can be held by a first capacitor provided in a second storage circuit. With the use of a transistor in which a channel is formed in an oxide semiconductor layer, a signal held in the first capacitor is held for a long time. The storage element can accordingly hold the stored content (data) also in a period during which the supply of the power supply voltage is stopped. A signal held by the first capacitor can be converted into the one corresponding to the state (the on state or off state) of the second transistor and read from the second storage circuit. Consequently, an original signal can be accurately read.
摘要翻译：提供能够抑制功耗的信号处理电路。在不向存储元件提供电源电压的期间中，存储在与非易失性存储器相对应的第一存储电路中的数据可以由设置在第二存储电路中的第一电容器保持。通过使用在氧化物半导体层中形成沟道的晶体管，保持在第一电容器中的信号被保持很长时间。因此，存储元件也可以在停止供给电源电压的期间保持存储的内容（数据）。可以将由第一电容器保持的信号转换为与第二晶体管的状态（导通状态或截止状态）对应的信号，并从第二存储电路读取。因此，可以准确地读取原始信号。

74. 发明申请

US20150108543A1 Source/Drain Structure of Semiconductor Device 审中-公开
标题翻译：半导体器件的源极/漏极结构
公开(公告)号：US20150108543A1
公开(公告)日：2015-04-23
申请号：US14579247
申请日：2014-12-22
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Ying Xiao
IPC分类号： H01L29/78 , H01L29/26 , H01L29/06
CPC分类号： H01L29/66636 , H01L29/0653 , H01L29/26 , H01L29/66575 , H01L29/66795 , H01L29/66878 , H01L29/7842 , H01L29/7848 , H01L29/785 , H01L29/7851
摘要： The disclosure relates to a semiconductor device. An exemplary structure for a field effect transistor comprises a substrate comprising a major surface and a cavity below the major surface; a gate stack on the major surface of the substrate; a spacer adjoining one side of the gate stack; a shallow trench isolations (STI) region disposed on the side of the gate stack, wherein the STI region is within the substrate; and a source/drain (S/D) structure distributed between the gate stack and STI region, wherein the S/D structure comprises a strained material in the cavity, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; and a S/D extension disposed between the substrate and strained material, wherein the S/D extension comprises a portion extending below the spacer and substantially vertical to the major surface.
摘要翻译：本公开涉及一种半导体器件。用于场效应晶体管的示例性结构包括：基底，其包括主表面和主表面下方的空腔; 在基板的主表面上的栅极堆叠; 邻接栅堆叠的一侧的间隔件; 设置在所述栅极堆叠侧的浅沟槽隔离（STI）区域，其中所述STI区域在所述衬底内; 以及分布在栅极堆叠和STI区域之间的源极/漏极（S / D）结构，其中S / D结构包括空腔中的应变材料，其中应变材料的晶格常数不同于晶体常数基质; 以及设置在所述基板和应变材料之间的S / D延伸部，其中所述S / D延伸部包括在所述间隔件下方延伸并且基本垂直于所述主表面的部分。

75. 发明授权

US09006736B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09006736B2
公开(公告)日：2015-04-14
申请号：US14321515
申请日：2014-07-01
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Shinya Sasagawa , Motomu Kurata
IPC分类号： H01L29/786 , H01L29/76 , H01L29/26
CPC分类号： H01L29/7869 , H01L29/24 , H01L29/247 , H01L29/263 , H01L29/42356 , H01L29/42364 , H01L29/78693 , H01L29/78696
摘要： To give favorable electrical characteristics to a semiconductor device. The semiconductor device includes an insulating layer, a semiconductor layer over the insulating layer, a pair of electrodes over the semiconductor layer and each electrically connected to the semiconductor layer, a gate electrode over the semiconductor layer, and a gate insulating layer between the semiconductor layer and the gate electrode. The insulating layer includes an island-shaped projecting portion. A top surface of the projecting portion of the insulating layer is in contact with a bottom surface of the semiconductor layer, and is positioned on an inner side of the semiconductor layer when seen from above. The pair of electrodes covers part of a top surface and part of side surfaces of the semiconductor layer. Furthermore, the gate electrode and the gate insulating layer cover side surfaces of the projecting portion of the insulating layer.
摘要翻译：为半导体器件提供有利的电气特性。半导体器件包括绝缘层，绝缘层上的半导体层，半导体层上的一对电极，并且各自电连接到半导体层，半导体层上的栅极电极以及半导体层之间的栅极绝缘层和栅电极。绝缘层包括岛形突出部分。绝缘层的突出部分的顶表面与半导体层的底表面接触，并且当从上方观察时位于半导体层的内侧。该对电极覆盖半导体层的顶表面和侧表面的一部分。此外，栅极电极和栅极绝缘层覆盖绝缘层的突出部分的侧表面。

76. 发明申请

US20150076488A1 THIN FILM TRANSISTOR 有权
标题翻译：薄膜晶体管
公开(公告)号：US20150076488A1
公开(公告)日：2015-03-19
申请号：US14391104
申请日：2013-06-06
申请人： KABUSHIKI KAISHA KOBE SEIKO SHO (Kobe Steel,Ltd.)
发明人： Tomoya Kishi , Kenta Hirose , Shinya Morita , Toshihiro Kugimiya
IPC分类号： H01L29/786 , H01L29/26 , H01L27/12
CPC分类号： H01L29/7869 , H01L21/02554 , H01L21/02565 , H01L21/02631 , H01L27/1225 , H01L29/26
摘要： Provided is a thin film transistor having an oxide semiconductor layer that has high mobility, excellent stress resistance, and good wet etching property. The thin film transistor comprises at least, a gate electrode, a gate insulating film, an oxide semiconductor layer, source-drain electrode and a passivation film, in this order on a substrate. The oxide semiconductor layer is a laminate comprising a first oxide semiconductor layer (IGZTO) and a second oxide semiconductor layer (IGZO). The second oxide semiconductor layer is formed on the gate insulating film, and the first oxide semiconductor layer is formed between the second oxide semiconductor layer and the passivation film. The contents of respective metal elements relative to the total amount of all the metal elements other than oxygen in the first oxide semiconductor layer are as follows; In: 25% or less (excluding 0%); Ga: 5% or more; Zn: 30.0 to 60.0%; and Sn: 8 to 30%.
摘要翻译：提供了具有高迁移率，优异的耐应力和良好的湿蚀刻性能的氧化物半导体层的薄膜晶体管。薄膜晶体管至少包括栅电极，栅极绝缘膜，氧化物半导体层，源 - 漏电极和钝化膜。氧化物半导体层是包括第一氧化物半导体层（IGZTO）和第二氧化物半导体层（IGZO）的层压体。第二氧化物半导体层形成在栅极绝缘膜上，第一氧化物半导体层形成在第二氧化物半导体层和钝化膜之间。各金属元素相对于第一氧化物半导体层中除氧以外的全部金属元素的总量的含量如下：在：25％以下（不包括0％）; Ga：5％以上; Zn：30.0〜60.0％和Sn：8〜30％。

77. 发明授权

US08980066B2 Thin film metal oxynitride semiconductors 有权
标题翻译：薄膜金属氧氮化物半导体
公开(公告)号：US08980066B2
公开(公告)日：2015-03-17
申请号：US12049017
申请日：2008-03-14
申请人： Yan Ye
发明人： Yan Ye
IPC分类号： C23C14/34 , C23C14/00 , C23C14/06 , H01J37/34 , H01L21/02 , H01L29/26 , H01L31/18 , H01L31/20 , H01L29/786
CPC分类号： C23C14/0063 , C23C14/0676 , H01J37/3408 , H01J37/3429 , H01L21/02521 , H01L21/0254 , H01L21/02554 , H01L21/02565 , H01L21/02573 , H01L21/02631 , H01L29/26 , H01L29/7869 , H01L31/18 , H01L31/20 , Y02E10/50
摘要： The present invention generally relates to a semiconductor film and a method of depositing the semiconductor film. The semiconductor film comprises oxygen, nitrogen, and one or more elements selected from the group consisting of zinc, cadmium, gallium, indium, and tin. Additionally, the semiconductor film may be doped. The semiconductor film may be deposited by applying an electrical bias to a sputtering target comprising the one or more elements selected from the group consisting of zinc, cadmium, gallium, indium, and tin, and introducing a nitrogen containing gas and an oxygen containing gas. The sputtering target may optionally be doped. The semiconductor film has a mobility greater than amorphous silicon. After annealing, the semiconductor film has a mobility greater than polysilicon.
摘要翻译：本发明一般涉及半导体膜和沉积半导体膜的方法。半导体膜包括氧，氮和选自锌，镉，镓，铟和锡中的一种或多种元素。此外，可以掺杂半导体膜。可以通过向包括选自锌，镉，镓，铟和锡中的一种或多种元素的溅射靶施加电偏压并引入含氮气体和含氧气体来沉积半导体膜。可以任选地掺杂溅射靶。该半导体膜的迁移率大于非晶硅。退火后，半导体膜的迁移率大于多晶硅。

78. 发明申请

US20140239293A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20140239293A1
公开(公告)日：2014-08-28
申请号：US14174438
申请日：2014-02-06
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Shunpei YAMAZAKI , Hideomi SUZAWA , Akihisa SHIMOMURA , Tetsuhiro TANAKA , Sachiaki TEZUKA
IPC分类号： H01L29/78 , H01L29/26
CPC分类号： H01L29/7869 , H01L29/105 , H01L29/26 , H01L29/41733 , H01L29/78 , H01L29/78693 , H01L29/78696
摘要： Disclosed is a semiconductor device including two oxide semiconductor layers, where one of the oxide semiconductor layers has an n-doped region while the other of the oxide semiconductor layers is substantially i-type. The semiconductor device includes the two oxide semiconductor layers sandwiched between a pair of oxide layers which have a common element included in any of the two oxide semiconductor layers. A double-well structure is formed in a region including the two oxide semiconductor layers and the pair of oxide layers, leading to the formation of a channel formation region in the n-doped region. This structure allows the channel formation region to be surrounded by an i-type oxide semiconductor, which contributes to the production of a semiconductor device that is capable of feeding enormous current.
摘要翻译：公开了包括两个氧化物半导体层的半导体器件，其中氧化物半导体层中的一个具有n掺杂区域，而另一个氧化物半导体层基本上是i型。半导体器件包括夹在一对氧化物层之间的两个氧化物半导体层，其具有包含在两个氧化物半导体层中的任一个中的共同元素。在包括两个氧化物半导体层和一对氧化物层的区域中形成双阱结构，导致在n掺杂区域中形成沟道形成区域。该结构允许沟道形成区域被i型氧化物半导体包围，这有助于生产能够馈送大量电流的半导体器件。

79. 发明授权

US08791469B2 Semiconductor light emitting element having a plurality of substrate cutouts and semiconductor layer side surface projections 有权
标题翻译：具有多个基板切口和半导体层侧面突起的半导体发光元件
公开(公告)号：US08791469B2
公开(公告)日：2014-07-29
申请号：US13693460
申请日：2012-12-04
申请人： Toyoda Gosei Co., Ltd.
发明人： Hironao Shinohara , Kensuke Hirano
IPC分类号： H01L27/15 , H01L29/26 , H01L31/12 , H01L33/00 , H01L33/20 , H01L33/22
CPC分类号： H01L33/20 , H01L33/005 , H01L33/0095 , H01L33/22 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/49107 , H01L2924/181 , H01L2924/00012 , H01L2924/00014
摘要： In a semiconductor light emitting element (1) having a sapphire substrate (100), and lower (210) and upper (220) semiconductor layers laminated on the sapphire substrate, the substrate includes a substrate top surface (113), a substrate bottom surface (114), first substrate side surfaces (111) and second substrate side surfaces (112); plural first (121a) and second (122a) cutouts are provided at a border between the first substrate side surface, the second substrate side surface and the substrate top surface; the lower semiconductor layer includes a lower semiconductor bottom surface, a lower semiconductor top surface (213), first lower semiconductor side surfaces (211) and second lower semiconductor side surfaces (212); plural first projecting portions (211a) and plural first depressing portions (211b) are provided on the first lower semiconductor side surface; and plural second protruding portions (212a) and second flat portions (212b) are provided on the second lower semiconductor side surface.
摘要翻译：在具有蓝宝石衬底（100）的半导体发光元件（1）和层叠在蓝宝石衬底上的下（210）和上（220）半导体层的衬底中，衬底包括衬底顶表面（113），衬底底表面（114），第一基板侧表面（111）和第二基板侧表面（112）; 多个第一（121a）和第二（122a）切口设置在第一基板侧表面，第二基板侧表面和基板顶表面之间的边界处; 下半导体层包括下半导体底表面，下半导体顶表面（213），第一下半导体侧表面（211）和第二下半导体侧表面（212）; 多个第一突出部分（211a）和多个第一按压部分（211b）设置在第一下部半导体侧表面上; 并且在第二下半导体侧面上设置有多个第二突出部（212a）和第二平坦部（212b）。

80. 发明申请

US20140106504A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20140106504A1
公开(公告)日：2014-04-17
申请号：US14054162
申请日：2013-10-15
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Shunpei YAMAZAKI , Hideomi SUZAWA , Shinya SASAGAWA , Tetsuhiro TANAKA
IPC分类号： H01L21/02 , H01L29/26 , H01L29/78 , H01L29/04
CPC分类号： H01L21/02565 , C23C14/086 , C23C14/3414 , H01L21/02488 , H01L21/02554 , H01L21/02592 , H01L21/02609 , H01L21/02617 , H01L21/02631 , H01L21/441 , H01L21/47576 , H01L21/47635 , H01L29/045 , H01L29/26 , H01L29/45 , H01L29/4908 , H01L29/66969 , H01L29/78 , H01L29/7869
摘要： To provide a semiconductor device in which an increase in oxygen vacancies is suppressed. To provide a semiconductor device with favorable electrical characteristics. To provide a highly reliable semiconductor device. In a semiconductor device in which a channel formation region is included in an oxide semiconductor layer, an oxide insulating film below and in contact with the oxide semiconductor layer and a gate insulating film over and in contact with the oxide semiconductor layer are used to supply oxygen of the gate insulating film, which is introduced by an ion implantation method, to the oxide semiconductor layer.
摘要翻译：提供抑制氧空位增加的半导体器件。提供具有良好电特性的半导体器件。提供高度可靠的半导体器件。在氧化物半导体层中包括沟道形成区域的半导体器件中，使用氧化物半导体层下方并与氧化物半导体层接触的氧化物绝缘膜和与氧化物半导体层接触并与氧化物半导体层接触的栅极绝缘膜供给氧通过离子注入法引入的栅极绝缘膜到氧化物半导体层。

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