专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明授权

US4753901A Two mask technique for planarized trench oxide isolation of integrated devices 失效
标题翻译：集成器件的平面化沟槽氧化物隔离的两种掩模技术
公开(公告)号：US4753901A
公开(公告)日：1988-06-28
申请号：US798511
申请日：1985-11-15
申请人： Daniel L. Ellsworth , Scott H. Cravens , Maurice M. Moll
发明人： Daniel L. Ellsworth , Scott H. Cravens , Maurice M. Moll
IPC分类号： H01L21/76 , H01L21/316 , H01L21/762 , H01L21/467
CPC分类号： H01L21/76229 , H01L21/31604 , Y10S148/05 , Y10S148/111
摘要： A two mask process for forming dielectrically filled planarized trenches of arbitrary width in a semiconductor substrate, the masks being of such character that they are amenable to computerized generation. The first mask defines the active regions and subdivides the trench isolation regions into a succession of trench and plateau regions, where the widths of the trench and plateau regions fall within in a dimensional range constrained by photolithographic precision of the masks and the ability to conformally deposit dielectric material into the trenches. With the first etch mask in place, the semiconductor is anisotropically etched to formed the first trench regions. A conformal deposition of dielectric follows, and by virtue of the dimensional constraints ensures substantially void free trench dielectric and a concluding substantially planar topology of the dielectric on the substrate surface. Following the etch of the deposited dielectric to the level of the plateau and active region surfaces, a second mask, defined to be slightly larger than the active regions, is formed over the substrate. A selective etch is then applied to remove the plateau regions and thereby form new trenches approximating in depth the first trenches. A second conformal deposition of dielectric follows, to fill the plateau region defined trenches in the manner of the first dielectric deposition. An etch of the second dielectric to the surface of the active regions follows to complete the fabrication. The substrate surface is planar and now divided into active regions which are separated by oxide filled, arbitrary width trenches.
摘要翻译：一种用于在半导体衬底中形成任意宽度的介电填充的平坦化沟槽的双掩模工艺，其掩模具有这样的特性，使得它们可以被计算机化生成。第一掩模限定有源区域并将沟槽隔离区域细分成一连串的沟槽和平台区域，其中沟槽和平台区域的宽度在由掩模的光刻精度限制的尺寸范围内，并且保形沉积的能力电介质材料进入沟槽。利用第一蚀刻掩模到位，半导体被各向异性蚀刻以形成第一沟槽区域。电介质的共形沉积跟随，并且由于尺寸约束确保基本无空隙的沟槽电介质和衬底表面上的电介质的结论基本上平面的拓扑结构。在沉积的电介质蚀刻到平台和有源区表面的水平之后，在衬底上方形成限定为略大于有源区的第二掩模。然后施加选择性蚀刻以去除平台区域，从而形成在第一沟槽深度近似的新的沟槽。电介质的第二共形沉积跟随，以第一介电沉积的方式填充平稳区域限定的沟槽。随后完成制造的第二电介质到有源区的表面的蚀刻。衬底表面是平面的，现在被划分成由氧化物填充的任意宽度的沟槽分开的有源区域。

72. 发明授权

US4694564A Method for the manufacture of a Schottky gate field effect transistor 失效
标题翻译：制造肖特基栅场效应晶体管的方法
公开(公告)号：US4694564A
公开(公告)日：1987-09-22
申请号：US887211
申请日：1986-07-21
申请人： Takatomo Enoki , Kimiyoshi Yamasaki , Kuniki Ohwada
发明人： Takatomo Enoki , Kimiyoshi Yamasaki , Kuniki Ohwada
IPC分类号： H01L29/812 , H01L21/285 , H01L21/338 , H01L21/467
CPC分类号： H01L29/66871 , H01L21/28587 , Y10S148/139
摘要： In the manufacture of a Schottky gate field effect transistor, an insulating film is deposited on the main surface of a semiconductor substrate and is then selectively removed to form therein a window through which the substrate surface region for forming an active layer is exposed to a space in which the gate will ultimately be provided. A metal which forms a Schottky junction between it and the semiconductor of the active layer and can be removed by anisotropic etching and a metal which can be used as a mask for the etching of the above metal are deposited in layers on the insulating film and the substrate surface exposed through the window. The overlying metal layer thus deposited is planarized to leave in the window alone. The underlying metal layer is selectively removed by anisotropic etching through the overlying metal layer remaining in the window, thus forming a gate electrode made up of the overlying and underlying metal layers. The structure thus obtained is small in the overlapping of the gate electrode on the adjoining insulating films, ensuring the reduction of parasitic capacitances to thereby speed up the operation of the device.
摘要翻译：在肖特基门场效应晶体管的制造中，绝缘膜沉积在半导体衬底的主表面上，然后被选择性地去除以形成窗口，用于形成有源层的衬底表面区域通过该窗口暴露于空间最终将提供门。在其与活性层的半导体之间形成肖特基结的金属，可以通过各向异性蚀刻除去，并且可以用作用于蚀刻上述金属的掩模的金属沉积在绝缘膜上，并且衬底表面通过窗户暴露。如此沉积的上覆金属层被平坦化，以在单独的窗口中离开。通过各向异性蚀刻通过残留在窗口中的上覆金属层选择性地去除底层金属层，从而形成由上覆和下面的金属层构成的栅电极。由此获得的结构在邻接的绝缘膜上的栅电极的重叠处小，确保了寄生电容的减小，从而加速了器件的工作。

73. 发明授权

US4414066A Electrochemical photoetching of compound semiconductors 失效
标题翻译：化学半导体的电化学光刻
公开(公告)号：US4414066A
公开(公告)日：1983-11-08
申请号：US416472
申请日：1982-09-10
申请人： Stephen R. Forrest , Paul A. Kohl , Richard L. Panock
发明人： Stephen R. Forrest , Paul A. Kohl , Richard L. Panock
IPC分类号： C25F3/12 , H01L21/3063 , H01L21/465 , H01L21/467
CPC分类号： H01L21/467 , C25F3/12 , H01L21/30635 , H01L21/465
摘要： A procedure is described for electrochemically photoetching n-type and intrinsic compound semiconductors. The process involves applying a potential to the compound semiconductor while it is in contact with an electrolytic solution and irradiating the surface to be etched with light in a certain energy range. By suitable adjustment in the potential, electrolytic solution composition and light energy, the etch rate is made proportional to the light intensity. By suitable variation in light intensity and light-ray direction, various geometrical features can be made on the surface of the compound semiconductor. For example, a hole with straight sides can be made in the compound semiconductor by use of a light spot and parallel (collimated) light rays. An advantageous application of this process is the fabrication of a photodiode with a hole in the center for use in bidirectional communication systems and to monitor power output for optical communication sources. The advantage of this process is that no damage occurs outside etched hole so that a maximum area of the photodiode remains active for detecting incoming radiation. Another advantage of the process is that etching will stop where the material becomes p-type so that etching can be made to stop automatically at a p/n junction.
摘要翻译：描述了用于电化学光刻n型和本征化合物半导体的方法。该方法包括在化合物半导体与电解液接触的同时施加电位，并在一定的能量范围内用光照射被蚀刻的表面。通过适当调整电位，电解液组成和光能，刻蚀速率与光强成正比。通过适当的光强度和光线方向的变化，可以在化合物半导体的表面上形成各种几何特征。例如，可以通过使用光点和平行（准直）光线在化合物半导体中制造具有直边的孔。该方法的有利应用是制造在中心具有用于双向通信系统的孔的光电二极管，并监视光通信源的功率输出。该方法的优点是在蚀刻孔外部不产生损伤，使得光电二极管的最大面积保持活跃以检测入射辐射。该方法的另一个优点是，在材料变为p型的情况下，蚀刻将停止，使得蚀刻可以在p / n结处自动停止。

74. 发明授权

US4178197A Formation of epitaxial tunnels utilizing oriented growth techniques 失效
标题翻译：利用定向生长技术形成外延隧道
公开(公告)号：US4178197A
公开(公告)日：1979-12-11
申请号：US17230
申请日：1979-03-05
申请人： John C. Marinace
发明人： John C. Marinace
IPC分类号： C30B25/18 , C30B29/40 , G01D15/18 , H01L21/20 , H01L21/205 , H01L23/473 , H01L27/14 , H01L29/04 , H01L29/06 , H01L31/00 , H01L31/0264 , H01L33/20 , H01L21/467 , H01L21/76
CPC分类号： H01L33/20 , G01D15/18 , H01L21/02395 , H01L21/02433 , H01L21/02532 , H01L21/02546 , H01L21/02639 , H01L21/0265 , H01L23/473 , H01L29/045 , H01L29/0657 , H01L29/0684 , H01L2924/0002
摘要： Epitaxial tunnels may be formed in crystalline bodies of crystalline materials by growth of the material on a substrate having two intersecting crystallographic planes that exhibit rapid epitaxial growth and by maintaining the growth until the structure forming along those planes closes, thereby producing a tunnel. P-n junction structures can be made in semiconductor devices by appropriate techniques.
摘要翻译：外延隧道可以通过在具有显示快速外延生长的两个相交结晶面的基板上生长材料并通过保持生长直到沿着这些平面形成的结构闭合从而产生隧道而在结晶材料的结晶体中形成。可以通过适当的技术在半导体器件中制造P-n结结构。

75. 发明授权

US3924265A Low capacitance V groove MOS NOR gate and method of manufacture 失效
公开(公告)号：US3924265A
公开(公告)日：1975-12-02
申请号：US39266873
申请日：1973-08-29
申请人： AMERICAN MICRO SYST
发明人： RODGERS THURMAN JOHN
IPC分类号： H01L21/764 , H01L21/8234 , H01L27/07 , H01L27/088 , H01L29/00 , H01L29/423 , H01L29/78 , H03K19/0944 , H01L27/04 , H01L21/467
CPC分类号： H03K19/09441 , H01L27/0738 , H01L27/088 , H01L29/00 , H01L29/4236 , Y10S148/008 , Y10S148/049 , Y10S148/051 , Y10S148/053 , Y10S148/085 , Y10S148/117
摘要： An MOS transistor is provided having a surface diffused drain and a common substrate source. A heavily doped base layer and a lightly doped space charge region are provided between the drain and source regions. The gate is formed on the inclined surface of a V groove which penetrates into the transistor to the substrate exposing the base layer to the gate structure. The gate is formed in the V groove by a silicon oxide insulative layer and conductive layer. Appropriate leads contact the gate conductor and the drain.

76. 发明授权

US12068171B2 Method for etching oxide semiconductor film and plasma processing apparatus 有权
公开(公告)号：US12068171B2
公开(公告)日：2024-08-20
申请号：US17163102
申请日：2021-01-29
申请人： TOKYO ELECTRON LIMITED
发明人： Masahiro Yamazaki , Shigeru Tahara
IPC分类号： H01L21/311 , H01J37/32 , H01L21/02 , H01L21/3213 , H01L21/465 , H01L21/467
CPC分类号： H01L21/467 , H01J37/32449 , H01J37/32715 , H01L21/02057 , H01L21/32136 , H01L21/465 , H01J37/32238 , H01J2237/334
摘要： A method for etching an oxide semiconductor film includes: providing a substrate including a mask of a silicon-containing film on an oxide semiconductor film containing at least indium (In), gallium (Ga), and zinc (Zn); supplying a processing gas containing a bromine (Br)-containing gas or an iodine (I)-containing gas; and etching the oxide semiconductor film by plasma generated from the processing gas.

77. 发明授权

US11211478B2 Semiconductor structure and method for forming same 有权
公开(公告)号：US11211478B2
公开(公告)日：2021-12-28
申请号：US16993689
申请日：2020-08-14
申请人： Semiconductor Manufacturing International (Shanghai) Corporation , Semiconductor Manufacturing International (Beijing) Corporation
发明人： Zheng Erhu , Liu Panpan
IPC分类号： H01L29/66 , H01L21/8234 , H01L21/308 , H01L21/265 , H01L21/033 , H01L21/322 , H01L29/78 , H01L21/467
摘要： A semiconductor structure and method for forming same are provided. The forming method includes: providing a base; forming a discrete core layer on the base; forming a spacer on a sidewall of the core layer; removing the core layer; after the core layer is removed, patterning the base using the spacer as a mask to form a fin, the fin including a device fin and a dummy fin; removing the spacer; performing doping removal on the dummy fin one or more times to remove the dummy fin, the step of the doping removal including: performing ion doping on the entire dummy fin or a part of the dummy fin in thickness for improving an etching selection ratio of the dummy fin to the device fin; and removing the ion-doped dummy fin. Embodiments and implementations of the present disclosure help increase a process window of a fin cut process.

78. 发明授权

US11087985B2 Manufacturing method of TFT array substrate 有权
公开(公告)号：US11087985B2
公开(公告)日：2021-08-10
申请号：US16319349
申请日：2018-12-11
申请人： Shenzhen China Star Optoelectronics Technology Co., Ltd.
发明人： Xiaodi Liu
IPC分类号： H01L21/033 , H01L27/12 , H01L21/308 , H01L21/3213 , H01L21/311 , H01L21/4763 , H01L21/467 , H01L21/4757 , H01L21/3065
摘要： The invention provides a manufacturing method of the TFT array substrate. Compared to existing 4M process, the invention changes the structural design of the semi-transmissive mask for the photoresist layer for patterning the source/drain metal layer and the semiconductor layer. The edge forms a reduced thickness edge portion, so that the edge of the photoresist layer is thinned, and thereby the width of the photoresist layer is easily reduced in subsequent processes, and the semiconductor layer at the edge of the metal wire structure is easily etched during dry etching, reducing the tailing problem of the active layer at edges of source/drain to achieve finer metal wire structure, and improve optical stability, electrical performance, aperture ratio, reliability, power consumption, and the overall performance of the TFT array substrate. The residual problem of amorphous and heavily doped silicon on source/drain edge in original process is solved or reduced.

79. 发明授权

US11018236B2 Thin film transistor, array substrate, display panel and method for manufacturing thin film transistor 有权
公开(公告)号：US11018236B2
公开(公告)日：2021-05-25
申请号：US16397386
申请日：2019-04-29
申请人： HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD. , BOE TECHNOLOGY GROUP CO., LTD.
发明人： Tongshang Su , Dongfang Wang , Ce Zhao , Bin Zhou , Liangchen Yan
IPC分类号： H01L29/45 , G03F7/16 , G03F7/20 , G03F7/26 , H01L21/02 , H01L21/441 , H01L21/467 , H01L21/4763 , H01L27/12 , H01L29/24 , H01L29/66 , H01L29/786 , H01L21/027
摘要： The present disclosure provides a thin film transistor, including a base substrate, an active layer and a source/drain, and a conductive layer. The active layer and an outer edge of the conductive layer are formed in the same etching process. The present disclosure further provides a method for manufacturing a thin film transistor, including forming an active material layer and a conductive material layer, forming a photoresist on the conductive material layer, exposing and developing the photoresist by means of a halftone mask, removing segments of the active material layer and the conductive material layer corresponding to a photoresist completely-removed region by a same etching process, partially removing the photoresist in a photoresist completely-retained region and completely removing the photoresist in a photoresist partially-retained region, and removing a segment of the conductive material layer corresponding to the photoresist partially-retained region.

80. 发明授权

US10784120B2 Laminate, etching mask, method of producing laminate, method of producing etching mask, and method of producing thin film transistor 有权
公开(公告)号：US10784120B2
公开(公告)日：2020-09-22
申请号：US16082479
申请日：2016-11-21
申请人： Japan Advanced Institute of Science and Technology , Sumitomo Seika Chemicals Co., Ltd.
发明人： Satoshi Inoue , Tatsuya Shimoda , Kazuhiro Fukada , Kiyoshi Nishioka
IPC分类号： B32B3/00 , H01L21/3213 , H01L29/786 , H01L21/02 , H01L21/467 , H01L29/66 , H01L21/027
摘要： A laminate by using a paste or solution containing aliphatic polycarbonates having an etching mask function is provided. A method of producing a laminate of the present invention includes a pattern forming step of forming a pattern 80 of a first oxide precursor layer in which a compound of metal to be oxidized into a metal oxide is dispersed in a solution containing a binder (possibly including inevitable impurities) made of aliphatic polycarbonates on an oxide layer 44 or on the second oxide precursor layer to be oxidized into the oxide layer 44; an etching step of, after the pattern forming step, etching the oxide layer 44 or the second oxide precursor layer that is not protected by the pattern 80; and a heating step of, after the etching step, heating the oxide layer 44 or the second oxide precursor layer, and the first oxide precursor layer to a temperature at which the binder is decomposed or higher.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式