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71. 发明授权

US5701266A Programming flash memory using distributed learning methods 失效
标题翻译：使用分布式学习方法编程闪存
公开(公告)号：US5701266A
公开(公告)日：1997-12-23
申请号：US760928
申请日：1996-12-06
申请人： Albert Fazio , Gregory E. Atwood , James O. Mi , Paul Ruby
发明人： Albert Fazio , Gregory E. Atwood , James O. Mi , Paul Ruby
IPC分类号： G11C11/56 , G11C27/00
CPC分类号： G11C11/5628 , G11C11/5621
摘要： In a memory device including an array of memory cells, each memory cell having more than two possible states, a method for programming a memory cell to a desired state. The method comprises a control engine programming a subset of the array of memory cells. Characterization information is determined from the step of programming the subset, wherein the characterization information indicates programming characteristics of a representative memory cell of the array of memory cells. The control engine then uses the characterization information to directly program the memory cell to approximately the desired state without performing a program verify operation.
摘要翻译：在包括存储器单元阵列的存储器件中，每个存储器单元具有两个以上的可能状态，一种用于将存储器单元编程到期望状态的方法。该方法包括编程存储器单元阵列的子集的控制引擎。从编程该子集的步骤确定表征信息，其中表征信息指示存储器单元阵列的代表性存储单元的编程特性。控制引擎然后使用表征信息直接将存储器单元编程到大致期望的状态，而不执行程序验证操作。

72. 发明授权

US5694357A Nonvolatile semiconductor memory device for storing multi-value data 失效
标题翻译：用于存储多值数据的非易失性半导体存储器件
公开(公告)号：US5694357A
公开(公告)日：1997-12-02
申请号：US649767
申请日：1996-05-15
申请人： Seiichi Mori
发明人： Seiichi Mori
IPC分类号： G11C17/00 , G11C11/56 , G11C16/02 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C27/00
CPC分类号： G11C16/349 , G11C11/5621 , G11C11/5628
摘要： Each of the cell transistors which constitute an EEPROM is set one of the first to fourth threshold voltages, to store one of four different data items. The first and fourth threshold voltages are the lowest and the highest of the four, respectively, and the second threshold voltage is lower than the third threshold voltage. Each cell transistor is set at a neutral threshold voltage when the charge-accumulating layer accumulates no charge. The neutral threshold voltage is higher than the second threshold voltage and lower than the third threshold voltage. The difference between the neutral threshold voltage and one of the four threshold voltages is so small that the self-field of the cell transistor has a low intensity.
摘要翻译：构成EEPROM的每个单元晶体管被设置为第一至第四阈值电压中的一个，以存储四个不同数据项之一。第一和第四阈值电压分别是四个中的最低和最高，并且第二阈值电压低于第三阈值电压。当电荷累积层不积累时，每个单元晶体管被设置在中性阈值电压。中性阈值电压高于第二阈值电压并低于第三阈值电压。中性阈值电压与四个阈值电压中的一个之间的差异非常小，使得单元晶体管的自电场具有低强度。

73. 发明授权

US5689453A Data storing apparatus having a memory capable of storing analog data 失效
标题翻译：具有能够存储模拟数据的存储器的数据存储装置
公开(公告)号：US5689453A
公开(公告)日：1997-11-18
申请号：US493621
申请日：1995-06-22
申请人： Masaaki Tsukagoshi
发明人： Masaaki Tsukagoshi
IPC分类号： G11C17/00 , G11C16/02 , G11C27/00
CPC分类号： G11C27/005
摘要： A D/A converter converts input "n" bit digital data into discrete analog data by assigning each of the voltage values V.sub.0 -V.sub.2.spsb.n.sub.-1 to each "n" bit digital data. A non-volatile memory capable of write and readout of analog data is used as a memory. The memory stores each analog data, which is represented by one of the voltage values V.sub.0 -V.sub.2.spsb.n.sub.--1 corresponding to each "n" bit digital data, into a memory cell. The analog data readout from the memory is supplied to an A/D converter to be converted into the original "n" bit digital data. Thus, digital data represented by a plural number of bits is stored in a single memory cell, and memory capacity can be increased with a simple structure. The memory is divided into two areas, that is, a read/write area which allows both reading and writing and a write restricted area to which writing is restricted. A write restriction circuit prohibits writing of analog data to the write restricted area. In this structure, a single memory functions as both a ROM and RAM.
摘要翻译：通过将每个电压值V0-V2n-1分配给每个“n”位数字数据，D / A转换器将输入“n”位数字数据转换成离散模拟数据。使用能够写入和读出模拟数据的非易失性存储器作为存储器。存储器将由每个“n”位数字数据对应的电压值V0-V2n-1之一表示的每个模拟数据存储到存储单元中。从存储器读出的模拟数据被提供给A / D转换器，以转换成原始的“n”位数字数据。因此，由多个位表示的数字数据被存储在单个存储单元中，并且可以以简单的结构来增加存储器容量。存储器被分为两个区域，即一个允许读写的读/写区和一个限制写入的写限制区。写入限制电路禁止将模拟数据写入写入限制区域。在这种结构中，单个存储器既用作ROM又用作RAM。

74. 发明授权

US5631941A Register circuit 失效
标题翻译：寄存器电路
公开(公告)号：US5631941A
公开(公告)日：1997-05-20
申请号：US558418
申请日：1995-11-16
申请人： Guoliang Shou , Sunao Takatori , Makoto Yamamoto
发明人： Guoliang Shou , Sunao Takatori , Makoto Yamamoto
IPC分类号： G06F7/49 , G06G7/25 , G11C11/56 , G11C27/00 , G11C27/04 , H03M1/42 , G11C19/00
CPC分类号： H03M1/42 , G06F7/49 , G06G7/25 , G11C11/56 , G11C27/00 , G11C27/04 , G11C19/00 , G11C7/16 , G11C8/04
摘要： A quantized voltage is held by a holding circuit or a feedback circuit connected to a quantizing circuit so that a multi-valued voltage is registered. In another embodiment, outputs of bi-stable circuits with stopwise thresholds are added with weights introduced by a capacitive coupling.
摘要翻译：量化电压由连接到量化电路的保持电路或反馈电路保持，从而登记多值电压。在另一个实施例中，具有逐步阈值的双稳态电路的输出加上由电容耦合引入的权重。

75. 发明授权

US5627392A Semiconductor structure for long term learning 失效
标题翻译：半导体结构长期学习
公开(公告)号：US5627392A
公开(公告)日：1997-05-06
申请号：US399966
申请日：1995-03-07
申请人： Christopher J. Diorio , Paul E. Hasler , Bradley A. Minch , Carver A. Mead
发明人： Christopher J. Diorio , Paul E. Hasler , Bradley A. Minch , Carver A. Mead
IPC分类号： G11C27/00 , H01L29/788
CPC分类号： G11C27/005 , H01L29/7885
摘要： A silicon MOS transistor with a time-varying transfer function is provided which may operate both as a single transistor analog learning device and as a single transistor non-volatile analog memory. The time-varying transfer function is achieved by adding or removing electrons from the fully insulated floating gate of an N-type MOS floating gate transistor. The transistor has a control gate capacitively coupled to the floating gate; it is from the perspective of this control gate that the transfer function of the transistor is modified. Electrons are removed from the floating gate via Fowler-Nordheim tunneling. Electrons are added to the floating gate via hot-electron injection.
摘要翻译：提供了具有时变传递函数的硅MOS晶体管，其可以同时作为单晶体管模拟学习装置和单晶体管非易失性模拟存储器操作。通过从N型MOS浮栅晶体管的完全绝缘的浮栅中添加或去除电子来实现时变传递函数。晶体管具有电容耦合到浮动栅极的控制栅极; 从该控制栅极的角度看，晶体管的传递函数被修改。电子通过Fowler-Nordheim隧道从浮动门去除。电子通过热电子注入添加到浮动栅极。

76. 发明授权

US5625583A Analog memory system having an integrated circuit frequency domain processor 失效
标题翻译：具有集成电路频域处理器的模拟存储器系统
公开(公告)号：US5625583A
公开(公告)日：1997-04-29
申请号：US471596
申请日：1995-06-06
申请人： Gilbert P. Hyatt
发明人： Gilbert P. Hyatt
IPC分类号： B60R16/02 , B60R16/037 , F21V23/00 , G01J1/42 , G01S7/52 , G01S15/89 , G02F1/133 , G03F9/00 , G04G99/00 , G05B15/00 , G05B19/35 , G05B19/408 , G05B19/409 , G05B19/4093 , G05B19/414 , G06F13/16 , G06J1/00 , G07G1/12 , G10L19/00 , G11C11/56 , G11C19/28 , G11C19/36 , G11C27/00 , G11C27/02 , G11C27/04 , H03H17/02 , G11C13/00
CPC分类号： B60R16/0373 , F21V23/00 , G01S15/897 , G01S15/8977 , G01S7/52026 , G02F1/13318 , G03F9/7049 , G03F9/7088 , G04G99/006 , G05B19/351 , G05B19/408 , G05B19/4083 , G05B19/4086 , G05B19/409 , G05B19/4093 , G05B19/414 , G05B19/4142 , G06F13/16 , G06J1/00 , G07G1/12 , G10L19/00 , G11C11/565 , G11C13/0033 , G11C16/3418 , G11C16/3431 , G11C19/287 , G11C19/36 , G11C27/00 , G11C27/024 , G11C27/04 , G11C7/1042 , H03H17/0291 , G05B2219/23094 , G05B2219/33182 , G05B2219/34023 , G05B2219/34098 , G05B2219/34471 , G05B2219/34472 , G05B2219/35262 , G05B2219/35263 , G05B2219/35373 , G05B2219/35381 , G05B2219/35431 , G05B2219/35436 , G05B2219/35453 , G05B2219/35472 , G05B2219/35554 , G05B2219/35588 , G05B2219/36152 , G05B2219/36227 , G05B2219/36333 , G05B2219/36366 , G05B2219/36379 , G05B2219/36395 , G05B2219/36502 , G05B2219/36503 , G05B2219/36506 , G05B2219/36546 , G05B2219/41021 , G05B2219/42237 , G05B2219/45214 , G05B2219/45215 , G05B2219/49221 , G05B2219/50047 , G05B2219/50048 , G05B2219/50083 , G05B2219/50151 , G11C13/04 , G11C7/16 , Y02P90/265
摘要： An optical system has an optical image projected on an analog memory, such as a CCD array, generating analog charge signals in the analog memory. The analog charge signals are processed with an analog to digital converter to generate digital information. The digital information is processed with an integrated circuit frequency domain processor to generate frequency domain information. The frequency domain information can be stored in an output memory and can be communicated to a remote location. An image can be displayed in response to the stored analog image information and in response to the frequency domain information. A machine can be controlled in response to the frequency domain information.
摘要翻译：光学系统具有投影在诸如CCD阵列的模拟存储器上的光学图像，在模拟存储器中产生模拟充电信号。模拟电荷信号用模数转换器处理以产生数字信息。数字信息用集成电路频域处理器处理，以产生频域信息。频域信息可以存储在输出存储器中并且可以被传送到远程位置。可以响应于存储的模拟图像信息并且响应于频域信息来显示图像。可以根据频域信息来控制机器。

77. 发明授权

US5606522A Non-volatile analog memory 失效
标题翻译：非易失性模拟存储器
公开(公告)号：US5606522A
公开(公告)日：1997-02-25
申请号：US575279
申请日：1995-12-20
申请人： Yong-Yoong Chai
发明人： Yong-Yoong Chai
IPC分类号： G11C27/00 , G11C11/34
CPC分类号： G11C27/005
摘要： An analog memory includes a cell array, a comparator, a mode selector, and a controller. The cell array includes a plurality of memory cells each having a control gate an injector, and a floating gate, and a first input part of a differential input stage. A first high-voltage pulse signal is applied to the control gate and a second high-voltage pulse signal is applied to the injector. Charges are injected into or are erased from the floating gate through the injector. The comparator has a differential input port whose first input is a reference voltage signal and whose second input is a floating gate voltage signal of one of the plurality of memory cells. The comparator compares and outputs the difference between the reference voltage signal and the floating gate voltage signal. The mode selector connects the output of the comparator to the first input, functions as a unit amplifier during a reading mode, and connects the external reference voltage signal to the first input of the comparator during a writing mode. The controller maintains a program enable state if the current state of the comparator output signal is the same as its previous state and maintains a program disable state if the current state is different from the previous state. The controller generates first and second high-voltage pulse signals according to the state of the comparator output signal. The analog memory reduces the programming voltage, allows for fast programming operations, and increases memory life.
摘要翻译：模拟存储器包括单元阵列，比较器，模式选择器和控制器。单元阵列包括多个存储单元，每个存储单元具有一个控制栅极，一个注入器，以及一个浮动栅极和一个差分输入级的第一个输入部分。将第一高电压脉冲信号施加到控制栅极，并将第二高压脉冲信号施加到喷射器。通过注射器将注入注入或从浮动栅中擦除。比较器具有差分输入端口，其第一输入端为参考电压信号，其第二输入端为多个存储单元之一的浮置栅极电压信号。比较器比较并输出参考电压信号和浮动栅极电压信号之间的差值。模式选择器将比较器的输出连接到第一个输入，在读取模式下用作单位放大器，并在写入模式期间将外部参考电压信号连接到比较器的第一个输入。如果比较器输出信号的当前状态与其先前状态相同，则控制器保持程序使能状态，如果当前状态与先前状态不同，则保持程序禁止状态。控制器根据比较器输出信号的状态产生第一和第二高电压脉冲信号。模拟存储器降低编程电压，允许快速编程操作，并增加存储器的使用寿命。

78. 发明授权

US5566125A Method and circuitry for storing discrete amounts of charge in a single memory element 失效
公开(公告)号：US5566125A
公开(公告)日：1996-10-15
申请号：US422066
申请日：1995-03-31
申请人： Albert Fazio , Gregory E. Atwood , James Q. Mi
发明人： Albert Fazio , Gregory E. Atwood , James Q. Mi
IPC分类号： G11C17/00 , G11C11/56 , G11C16/02 , G11C27/00 , G11C13/00
CPC分类号： G11C27/005 , G11C11/5621 , G11C11/5628 , G11C11/565 , G11C2211/5621
摘要： A method and circuitry for programming a memory cell to one of at least three amounts of charge. The amount of charge placed in the memory cell is increased by increasing the voltage level of a programming pulse applied to the memory cell.

79. 发明授权

US5541878A Writable analog reference voltage storage device 失效
标题翻译：可写模拟参考电压存储器件
公开(公告)号：US5541878A
公开(公告)日：1996-07-30
申请号：US267595
申请日：1994-06-27
申请人： John LeMoncheck , Timothy P. Allen , Gunter Steinbach , Carver A. Mead
发明人： John LeMoncheck , Timothy P. Allen , Gunter Steinbach , Carver A. Mead
IPC分类号： G05F1/46 , G05F3/24 , G11C5/14 , G11C11/56 , G11C27/00 , G11C16/04
CPC分类号： G05F3/247 , G05F1/468 , G05F3/24 , G11C11/56 , G11C11/5621 , G11C27/005 , G11C5/147 , G11C16/30 , G11C2211/5634 , G11C7/16
摘要： A circuit for generating N analog voltage signals for reference or bias use employs N analog floating gate storage devices. Circuitry is provided so that all floating gate storage devices can be programmed to their target voltages individually or in parallel. Electron injection circuitry is provided for injecting electrons on to and a tunneling structure is provided for removing electrons from the floating gate of each floating gate storage device. A transistor structure with a lightly doped drain is provided for control of the tunneling structure. A capacitor is connected to each floating gate node to provide control of the injection structure. A dynamic analog storage element is provided to store the target voltage for the floating gate storage device. A comparator is provided to monitor the floating gate voltage and target voltage and control tunneling and injection. A digital storage device is provided to statically store the output of the comparator. During normal operation of the voltage reference circuit, the voltage comparator is configured as a follower amplifier to buffer the analog voltage output. During normal operation of the bias reference circuit, the current comparator is configured as a current mirror to buffer the analog current output.
摘要翻译：用于产生用于参考或偏置使用的N个模拟电压信号的电路使用N个模拟浮动栅极存储装置。提供电路，使得所有浮动栅极存储装置可以单独地或并行地编程到它们的目标电压。提供电子注入电路用于将电子注入到上面，并且提供隧道结构用于从每个浮动栅极存储装置的浮动栅极去除电子。提供了具有轻掺杂漏极的晶体管结构，用于控制隧道结构。电容器连接到每个浮动栅极节点以提供对注入结构的控制。提供动态模拟存储元件以存储浮动栅极存储装置的目标电压。提供一个比较器来监控浮动栅极电压和目标电压，并控制隧道和注入。提供数字存储设备以静态存储比较器的输出。在电压基准电路正常工作期间，电压比较器被配置为跟随放大器以缓冲模拟电压输出。在偏置参考电路的正常工作期间，电流比较器被配置为电流镜以缓冲模拟电流输出。

80. 发明授权

US5504699A Nonvolatile magnetic analog memory 失效
标题翻译：非易失磁性模拟存储器
公开(公告)号：US5504699A
公开(公告)日：1996-04-02
申请号：US224907
申请日：1994-04-08
申请人： Stuart E. Goller , Frank Powell
发明人： Stuart E. Goller , Frank Powell
IPC分类号： G11B20/00 , G11B23/00 , G11C27/00 , G11C13/00
CPC分类号： G11C27/00 , G11B20/00086 , G11B23/0042
摘要： A nonvolatile analog magnetic memory includes a substrate comprised of saturable and desaturable magnetic domains at distinguishable fixed locations, a bi-directional drive circuit to selectively write data to the magnetic domains by first saturating a selected magnetic domain with current flowing in one direction, followed by desaturating the magnetic domain with current flowing in the reverse direction of the saturating current, lowering the magnetic flux density to a level corresponding to the magnitude of an analog input electrical signal within a range of magnetic flux density levels between a zero point and a full scale point, sensors and a sensor select circuit to select a magnetic domain and nondestructively respond to the magnitude of the magnetic flux for the chosen magnetic domain, producing an electrical output signal corresponding to the magnetic flux for the chosen magnetic domain. A second embodiment includes a rotatable substrate, a bi-directional drive circuit on a read/write head sensor and a sensor select circuit. In both embodiments superconductive materials can be incorporated into the magnetic domain material, the bi-directional drive circuit, and sensors and sensor select circuitry. All components of the nonvolatile analog magnetic memory can be formed through photo-lithographic techniques, sputtering, and machine, electromechanical, or manual assembly. Cells of magnetic domain material can be arranged in both serial and parallel form for analog nonvolatile writing and reading.
摘要翻译：非易失性模拟磁存储器包括由可分辨的固定位置处的可饱和和不可磁化的磁畴组成的衬底;双向驱动电路，用于通过首先使选定的磁畴饱和所选择的磁畴，使电流沿一个方向流动，从而选择性地将数据写入磁畴，在饱和电流的相反方向流过电流对磁畴进行去饱和，将磁通密度降低到与零点和满量程之间的磁通密度水平范围内的模拟输入电信号的大小相对应的水平点，传感器和传感器选择电路，以选择磁畴并且非破坏地地响应所选磁畴的磁通量的大小，产生对应于所选磁畴的磁通量的电输出信号。第二实施例包括可旋转基板，读/写头传感器上的双向驱动电路和传感器选择电路。在两个实施例中，超导材料可以并入到磁畴材料，双向驱动电路以及传感器和传感器选择电路中。非易失性模拟磁存储器的所有组件可以通过光刻技术，溅射和机械，机电或手动组装来形成。磁畴材料的单元可以串行和并行布置，用于模拟非易失性写入和读取。

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