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71. 发明授权

US5047657A Integrated circuit comprising a signal level converter 失效
标题翻译：集成电路包括信号电平转换器
公开(公告)号：US5047657A
公开(公告)日：1991-09-10
申请号：US402002
申请日：1989-09-01
申请人： Evert Seevinck , Jan Dikken , Hans-Jurgen O. Schumacher
发明人： Evert Seevinck , Jan Dikken , Hans-Jurgen O. Schumacher
IPC分类号： G11C11/417 , H03K5/02 , H03K19/003 , H03K19/017 , H03K19/0185
CPC分类号： H03K19/00384 , H03K19/01707
摘要： An integrated circuit which includes a converter for converting a logic input signal of a first logic type into a logic output signal of a second logic type, for example, from ECL to CMOS level. The converter comprises a buffer, including a controllable load and a driver transistor, and a control circuit. The load is controlled as a function of a control voltage and a reference voltage which are externally applied so that the output signal is substantially equal to the reference voltage if the input signal is substantially equal to the control voltage. In one embodiment the control circuit is a copy of the buffer and receives the control voltage at its input. Its load is controlled by a differential amplifier whose inputs receive the reference voltage and the output voltage of the control circuit. A CMOS-SRAM comprising ECL/CMOS level converters of the above kind communicates with fast ECL circuits and has a low energy consumption.

72. 发明授权

US5004939A CMOS-ECL converter 失效
标题翻译： CMOS-ECL转换器
公开(公告)号：US5004939A
公开(公告)日：1991-04-02
申请号：US524443
申请日：1990-05-17
申请人： Michael Stegherr
发明人： Michael Stegherr
IPC分类号： H03K5/02 , H03K19/0175
CPC分类号： H03K19/017518
摘要： A CMOS-ECL converter contains a drive stage modified from the prior art and a connected output transistor. The driver stage comprises a resistor element and an n-channel field effect transistor. The resistor element can preferably be constructed with the assistance of a p-channel field effect transistor and is connected in series with the n-channel field effect transistor. The advantage of such an arrangement is that the capacitive load at the input of the CMOS-ECL converter is low because the resistor element or, respectively, the p-channel field effect transistor, offers no contribution to such an input load. The channel width of the p-channel field effect transistor can be set such that an adequately-high base current for the bipolar output transistor can be supplied.
摘要翻译： CMOS-ECL转换器包含从现有技术修改的驱动级和连接的输出晶体管。驱动器级包括电阻元件和n沟道场效应晶体管。电阻元件优选地可以在p沟道场效应晶体管的辅助下构成，并与n沟道场效应晶体管串联连接。这种布置的优点在于，CMOS-ECL转换器的输入处的电容性负载较低，因为电阻元件或分别为p沟道场效应晶体管对这种输入负载没有贡献。可以设置p沟道场效应晶体管的沟道宽度，使得可以提供用于双极性输出晶体管的足够高的基极电流。

73. 发明授权

US4996449A Output circuit having high speed operation and low power dissipation 失效
标题翻译：输出电路具有高速运行和低功耗
公开(公告)号：US4996449A
公开(公告)日：1991-02-26
申请号：US380335
申请日：1989-07-17
申请人： Masaji Ueno
发明人： Masaji Ueno
IPC分类号： H03K5/02 , H03K19/00 , H03K19/017 , H03K19/0175 , H03K19/0944
CPC分类号： H03K19/09448 , H03K19/0013 , H03K19/01721
摘要： There is provided an improved output circuit having high speed operation and low power dissipation. The circuit having MOS pull up and pull down transistors, wherein a control signal to the pull down MOS is delayed to discharge parasitic capacitance and to prevent both MOS transistors from being on simultaneously.

74. 发明授权

US4992755A Transistor circuit 失效
标题翻译：晶体管电路
公开(公告)号：US4992755A
公开(公告)日：1991-02-12
申请号：US467340
申请日：1990-01-19
申请人： Evert Seevinck , Jan Dikken , Hans-Jurgen Schumacher
发明人： Evert Seevinck , Jan Dikken , Hans-Jurgen Schumacher
IPC分类号： H03K5/02 , H03F1/32 , H03F3/45 , H03K19/003 , H03K19/0185
CPC分类号： H03K19/00361 , H03F1/3211 , H03F3/4565 , H03F3/45654 , H03F3/45659 , H03K19/018521 , H03F2203/45394
摘要： A transistor circuit comprising a first differential amplifier which is composed of a differential pair and a current mirror. The transistor circuit further comprises a second differential amplifier which measures a differential offset voltage in the first differential amplifier and reduces this offset voltage by means of common mode current feedback. The transistor circuit thus provides a stable amplifier having a high speed and a low offset voltage which can be used advantageously in a logic output buffer so that, for example, an ECL output buffer can be realized in CMOS.

75. 发明授权

US4992681A Logic level converting circuit 失效
标题翻译：逻辑电平转换电路
公开(公告)号：US4992681A
公开(公告)日：1991-02-12
申请号：US451316
申请日：1989-12-15
申请人： Yukihiro Urakawa , Masataka Matsui
发明人： Yukihiro Urakawa , Masataka Matsui
IPC分类号： H03K5/02 , H03K3/356 , H03K19/0175 , H03K19/0185 , H03K19/08
CPC分类号： H03K3/356069 , H03K3/356052 , H03K3/356147
摘要： A logic level converting circuit for converting an ECL level signal to a CMOS level signal comprises complementary signal generating means and level shifting means. The complementary signal generating means generates complementary signals in response to the ECL level input signal and a first reference voltage. The level shifting means operates as a flip-flop circuit, and includes a first and a second PMOS transistors which are either conductive or not conductive in response to the relationship between the complementary signals and a second reference voltage applied to the gate electrodes of the PMOS transistors.
摘要翻译：用于将ECL电平信号转换为CMOS电平信号的逻辑电平转换电路包括互补信号产生装置和电平转换装置。互补信号发生装置响应于ECL电平输入信号和第一参考电压产生互补信号。电平移动装置用作触发器电路，并且包括响应于互补信号之间的关系导通或不导电的第一和第二PMOS晶体管，以及施加到PMOS的栅电极的第二参考电压晶体管。

76. 发明授权

US4972517A Driver circuit receiving input voltage and providing corresponding output voltage 失效
标题翻译：驱动电路接收输入电压并提供相应的输出电压
公开(公告)号：US4972517A
公开(公告)日：1990-11-20
申请号：US318284
申请日：1989-03-03
申请人： Harufusa Kondou , Takeo Nakabayashi
发明人： Harufusa Kondou , Takeo Nakabayashi
IPC分类号： H03K5/02 , H03K5/24 , H03K17/687 , H03K19/0185 , H03K19/0948 , H04L25/02 , H04L25/08
CPC分类号： H04L25/08 , H03K19/018578 , H03K5/2481
摘要： A first comparator compares a voltage of a pair of primary terminals of a pulse transformer with a first reference voltage, to apply an output voltage corresponding to the voltage difference therebetween to a gate of an N channel MOSFET. The N channel MOSFET is responsive to the output voltage for controlling current flowing through a primary side of a pulse transformer. Consequently, even if the impedance of a load connector to a pair of secondary terminals of the pulse transformer is fluctuated, a voltage between the pair of secondary terminals is kept constant. A second comparator compares the output voltage of the first comparator with a second reference voltage, to apply an output voltage corresponding to the voltage difference therebetween to a gate of a P channel MOSFET. When the load impedance becomes low, the P channel MOSFET performs control such that the output voltage of the second comparator does not exceed a predetermined value. Consequently, current flowing through the primary side of the pulse transformer is limited not to exceed a constant value. Thus, a voltage between output terminals does not exceed a constant value.
摘要翻译：第一比较器将脉冲变压器的一对初级端子的电压与第一参考电压进行比较，以将对应于其电压差的输出电压施加到N沟道MOSFET的栅极。 N沟道MOSFET响应于输出电压来控制流过脉冲变压器初级侧的电流。因此，即使负载连接器对脉冲变压器的一对二次端子的阻抗波动，一对次端子之间的电压保持恒定。第二比较器将第一比较器的输出电压与第二参考电压进行比较，以将对应于其电压差的输出电压施加到P沟道MOSFET的栅极。当负载阻抗变低时，P沟道MOSFET进行控制使得第二比较器的输出电压不超过预定值。因此，流过脉冲变压器的初级侧的电流被限制为不超过常数值。因此，输出端子之间的电压不超过常数值。

77. 发明授权

US4945395A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US4945395A
公开(公告)日：1990-07-31
申请号：US449435
申请日：1989-12-11
申请人： Yoshiyuki Suehiro
发明人： Yoshiyuki Suehiro
IPC分类号： H01L21/822 , H01L21/60 , H01L27/04 , H01L27/118 , H03K5/02 , H03K19/173
CPC分类号： H01L24/06 , H01L27/11898 , H03K19/1735 , H03K5/026 , H01L2224/05554 , H01L2224/49171 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01033 , H01L2924/01039 , H01L2924/01074 , H01L2924/01082 , H01L2924/13091 , H01L2924/14 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011
摘要： A semiconductor circuit comprises basic cells formed in an internal cell region on an integrated-circuit chip and pads for input/output cells, the pads being arranged in peripheral regions on said chip. The semiconductor circuit further comprises first logic circuit means provided for each of the input/output cells, each including logic circuits formed by transistors of relatively high drive capability which are a part of said respective input/output cells, the first logic circuit means being positioned in the perpheral regions. The present invention also comprises second logic circuit means provided for each of the input/output cells, each including remaining logic circuits of the respective input/output cells, the second logic circuit being formed by the basic cells formed in the internal cell regions, so that each of said input/output cells is formed by one pad and the combination of the first and second logic circuit means.
摘要翻译：半导体电路包括形成在集成电路芯片上的内部单元区域中的基本单元和用于输入/输出单元的焊盘，所述焊盘布置在所述芯片上的外围区域中。半导体电路还包括为每个输入/输出单元提供的第一逻辑电路装置，每个单元包括由作为所述相应输入/输出单元的一部分的较高驱动能力的晶体管形成的逻辑电路，第一逻辑电路装置被定位在永久地区。本发明还包括为每个输入/输出单元提供的第二逻辑电路装置，每个单元包括各个输入/输出单元的剩余逻辑电路，第二逻辑电路由形成在内部单元区域中的基本单元形成，因此每个所述输入/输出单元由一个焊盘和第一和第二逻辑电路装置的组合形成。

78. 发明授权

US4929853A Input translating circuit for CMOS device 失效
标题翻译： CMOS器件的输入转换电路
公开(公告)号：US4929853A
公开(公告)日：1990-05-29
申请号：US342923
申请日：1989-04-25
申请人： Byeng-yun Kim , Yong-bo Park
发明人： Byeng-yun Kim , Yong-bo Park
IPC分类号： H03K5/02 , H03K19/00 , H03K19/003 , H03K19/0185
CPC分类号： H03K19/018521 , H03K19/00384
摘要： An input translating circuit for a CMOS device is disclosed which can be operated without being influenced by a level of the supply voltage. This is made possible by providing a supply voltage level discriminating means consisting of a voltage dividing network for dividing the supply voltage into predetermined voltages and a level comparing means for comparing the divided voltage with the reference voltage level, and further by providing a constant voltage supply means, so that a trip voltage, used in the operation of the circuit, can be maintained at a constant level regardless of the variations of the supply voltage. Further, the circuit according to the present invention eliminates corresponding mask work requirements for the option of the power voltage in the manufacturing process, thereby lowering production complexity costs.
摘要翻译：公开了一种用于CMOS器件的输入转换电路，其可以在不受电源电压水平的影响的情况下操作。这可以通过提供一种由分压网络组成的电源电压鉴别装置，用于将电源电压分成预定电压;以及电平比较装置，用于将分压电压与参考电压电平进行比较，并且进一步通过提供恒定电压源意味着，无论电源电压的变化如何，在电路的操作中使用的跳闸电压都可以保持在恒定的电平。此外，根据本发明的电路消除了在制造过程中对电源电压的选择的相应的掩模工作要求，从而降低了生产复杂度的成本。

79. 发明授权

US4902911A Semiconductor integrated circuit having a built-in power voltage generator 失效
标题翻译：具有内置电源电压发生器的半导体集成电路
公开(公告)号：US4902911A
公开(公告)日：1990-02-20
申请号：US245859
申请日：1988-09-19
申请人： Katsuji Hoshi
发明人： Katsuji Hoshi
IPC分类号： H03K5/02 , G06F1/10 , G06F1/26 , G11C11/407 , H03K19/00
CPC分类号： G06F1/10 , G06F1/26
摘要： A semiconductor integrated circuit having a voltage generator circuit for generating an internal power voltage lower than an externally supplied power voltage, a control circuit for generating at least one control signal and a functional circuit operating with the internal power voltage and controlled by the control signal is disclosed and featured in that the control circuit includes a first circuit operating with the externally supplied power voltage and generating a first signal with a predetermined timing relationship with respect to an input control signal thereto and a second circuit operating with the internal voltage and generating a second signal in response to the first signal, as the control signal for the functional circuit.

80. 发明授权

US4871686A Integrated Schottky diode and transistor 失效
标题翻译：集成肖特基二极管和晶体管
公开(公告)号：US4871686A
公开(公告)日：1989-10-03
申请号：US173795
申请日：1988-03-28
申请人： Robert B. Davies
发明人： Robert B. Davies
IPC分类号： H01L29/73 , H01L21/329 , H01L21/331 , H01L21/8222 , H01L21/8249 , H01L27/06 , H01L27/07 , H01L29/47 , H01L29/732 , H01L29/872 , H03K5/02 , H03K17/06
CPC分类号： H01L29/66212 , H01L21/8222 , H01L21/8249 , H01L27/0766 , H01L29/872 , H03K17/06 , H03K17/063
摘要： An improved means and method is described for forming a Schottky diode integrated with transistors and other devices which is particularly useful where both control circuits and a large power device are on the same chip.Nested N-, P-, N- and P+ regions are formed on an N+ semiconductor substrate. A portion of the overlying dielectric is removed adjacent one of the P+ regions over the N- region and a Schottky contact formed to the N- region and an ohmic contact to the adjacent P+ region. N+ and P+ regions are desirably provided where the junctions between the N-/P- regions and the P-/N- regions intersect the surface to provide contact to the N- and P- regions respectively.A P region extends through the upper N- region and has U-shaped arms which partially overlie an annular shaped P+ region and is located between the active region of the PNP transistor and the collector contact to serve as a Kelvin probe. The arrangement is particularly valuable where a vertical PNP device without a buried collector region is required.

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