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71. 发明申请

US20210242240A1 SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME 有权
公开(公告)号：US20210242240A1
公开(公告)日：2021-08-05
申请号：US16904557
申请日：2020-06-18
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： BO-FENG YOUNG , HAN-JONG CHIA , SAI-HOOI YEONG , YU-MING LIN , CHUNG-TE LIN
IPC分类号： H01L27/11597 , H01L27/06 , H01L23/48 , H01L27/11 , H01L27/1159 , H01L27/11592 , H01L29/78 , H01L29/66 , H01L21/768 , H01L21/822
摘要： The present disclosure provides a semiconductor structure, including: a first layer including a logic device; and a second layer over the first layer, including a first type memory device, a though silicon via (TSV) electrically connecting the logic device and the first type memory device. A method of forming semiconductor structure is also disclosed.

72. 发明申请

US20210217775A1 CROSS-POINT ARRAY OF FERROELECTRIC FIELD EFFECT TRANSISTORS AND METHOD OF MAKING THE SAME 有权
公开(公告)号：US20210217775A1
公开(公告)日：2021-07-15
申请号：US16738644
申请日：2020-01-09
申请人： SANDISK TECHNOLOGIES LLC
发明人： Yanli ZHANG , Johann ALSMEIER , Fei ZHOU
IPC分类号： H01L27/11597 , H01L27/11587 , H01L29/78 , H01L29/66 , G11C11/22
摘要： A semiconductor structure includes layer stack structures laterally extending along a first horizontal direction and spaced apart from each other along a second horizontal direction by line trenches. Each of the layer stack structures includes at least one instance of a unit layer sequence that includes, from bottom to top or top to bottom, a doped semiconductor source strip, a channel-level insulating strip, and a doped semiconductor drain strip. Line trench fill structures are located within a respective one of the line trenches. Each of the line trench fill structures includes a laterally-alternating sequence of memory pillar structures and dielectric pillar structures. Each of the memory pillar structures includes a gate electrode, at least one pair of ferroelectric dielectric layers, and at least one pair of vertical semiconductor channels located at each level of the channel-level insulating strips.

73. 发明授权

US11049880B2 Three-dimensional memory device containing epitaxial ferroelectric memory elements and methods for forming the same 有权
公开(公告)号：US11049880B2
公开(公告)日：2021-06-29
申请号：US16530256
申请日：2019-08-02
申请人： SANDISK TECHNOLOGIES LLC
发明人： Adarsh Rajashekhar , Fei Zhou , Rahul Sharangpani , Raghuveer S. Makala
IPC分类号： H01L27/11597 , H01L27/1157 , H01L27/11582 , H01L27/11587 , H01L27/11565 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/1159
摘要： A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack. Each of the memory stack structures includes a vertical stack of single crystalline ferroelectric dielectric layers and a respective vertical semiconductor channel.

74. 发明申请

US20210184044A1 Programmable Charge-Storage Transistor, An Array Of Elevationally-Extending Strings Of Memory Cells, And A Method Of Forming An Array Of Elevationally-Extending Strings Of Memory Cells 有权
公开(公告)号：US20210184044A1
公开(公告)日：2021-06-17
申请号：US17170082
申请日：2021-02-08
申请人： Micron Technology, Inc.
发明人： Haitao Liu , Kamal M. Karda , Albert Fayrushin
IPC分类号： H01L29/78 , H01L29/423 , H01L27/11582 , H01L29/51 , H01L27/11556 , H01L21/28 , H01L27/11597 , H01L29/792 , H01L27/1157 , H01L27/1159 , H01L29/66
摘要： A programmable charge-storage transistor comprises channel material, insulative charge-passage material, charge-storage material, a control gate, and charge-blocking material between the charge-storage material and the control gate. The charge-blocking material comprises a non-ferroelectric insulator material and a ferroelectric insulator material. Arrays of elevationally-extending strings of memory cells of memory cells are disclosed, including methods of forming such. Other embodiments, including method, are disclosed.

75. 发明申请

US20210175254A1 THREE-DIMENSIONAL FERROELECTRIC MEMORY 有权
公开(公告)号：US20210175254A1
公开(公告)日：2021-06-10
申请号：US17112475
申请日：2020-12-04
申请人： IMEC vzw
发明人： Jan Van Houdt
IPC分类号： H01L27/11597 , H01L27/1159
摘要： The disclosed technology relates generally to semiconductor memory devices, and more particularly to three-dimensional (3D) ferroelectric memory devices, methods of fabricating 3D ferroelectric memory devices, and methods of conditioning 3D ferroelectric memory devices. The 3D ferroelectric memory device exploits programmed memory cells as selector devices. In one aspect, a 3D ferroelectric memory device comprises a stack comprising a plurality of gate electrode layers and spacer layers, which are alternatingly arranged. The 3D ferroelectric memory device additionally comprises a semiconductor channel extending through the stack and a ferroelectric layer arranged between the gate electrode layers and the semiconductor channel. The gate electrode layers form, in combination with the channel and the ferroelectric layer, a string of ferroelectric transistors, wherein each ferroelectric transistor is associated with one cell of the memory device. The first ferroelectric transistor and the last ferroelectric transistor in the string have a lower threshold voltage than the other ferroelectric transistors.

76. 发明申请

US20210175253A1 NONVOLATILE MEMORY DEVICE HAVING A FERROELECTRIC LAYER 有权
公开(公告)号：US20210175253A1
公开(公告)日：2021-06-10
申请号：US16891544
申请日：2020-06-03
申请人： SK hynix Inc.
发明人： Jae Hyun HAN , Jae Gil LEE , Hyangkeun YOO , Se Ho LEE
IPC分类号： H01L27/11597 , H01L27/11587
摘要： A nonvolatile memory device according to an embodiment includes a substrate having an upper surface, and a gate structure disposed over the substrate. The gate structure includes at least one gate electrode layer pattern and at least one gate insulation layer pattern, which are alternately stacked along a first direction perpendicular to the upper surface. The gate structure extends in a second direction perpendicular to the first direction. The nonvolatile memory device includes a ferroelectric layer disposed on at least a portion of one sidewall surface of the gate structure. The one sidewall surface of the gate structure forms a plane substantially parallel to the first and second directions. The nonvolatile memory device includes a channel layer disposed on the ferroelectric layer, and a source electrode structure and a drain electrode structure disposed to contact the channel layer and spaced apart from each other in the second direction.

77. 发明申请

US20210126014A1 SEMICONDUCTOR DEVICE 有权
公开(公告)号：US20210126014A1
公开(公告)日：2021-04-29
申请号：US16989160
申请日：2020-08-10
申请人： Samsung Electronics Co., Ltd.
发明人： JINTAE KIM , HA-YOUNG KIM , SINWOO KIM , MOO-GYU BAE , JAEHA LEE
IPC分类号： H01L27/11597 , H01L27/108
摘要： Disclosed is a semiconductor device comprising a logic cell that is on a substrate and includes first and second active regions spaced apart from each other in a first direction, first and second active patterns that are respectively on the first and second active regions and extend in a second direction intersecting the first direction, gate electrodes extending in the first direction and running across the first and second active patterns, first connection lines that are in a first interlayer dielectric layer on the gate electrodes and extend parallel to each other in the second direction, and second connection lines that are in a second interlayer dielectric layer on the first interlayer dielectric layer and extend parallel to each other in the first direction.

78. 发明申请

US20210082958A1 MEMORY CELL ARRANGEMENT AND METHODS THEREOF 有权
公开(公告)号：US20210082958A1
公开(公告)日：2021-03-18
申请号：US16929660
申请日：2020-07-15
申请人： Ferroelectric Memory GmbH
发明人： Menno Mennenga , Johannes Ocker
IPC分类号： H01L27/11597 , H01L27/11587 , H01L27/11504 , G11C11/22 , H01L27/11514
摘要： A memory cell arrangement is provided that may include: a plurality of electrode layers, wherein each of the plurality of electrode layers comprises a plurality of through holes, each of the plurality of through holes extending from a first surface to a second surface of the respective electrode layer; a plurality of electrode pillars, wherein each of the plurality of electrode pillars comprises a plurality of electrode portions, wherein each of the plurality of electrode portions is disposed within a corresponding one of the plurality of through holes; wherein at least one remanent-polarizable portion is disposed in each of the plurality of through holes in a gap between the respective electrode layer and the respective electrode portion.

79. 发明申请

US20210082955A1 THREE-DIMENSIONAL MEMORY DEVICE CONTAINING FERROELECTRIC MEMORY ELEMENTS ENCAPSULATED BY TRANSITION METAL-CONTAINING CONDUCTIVE ELEMENTS AND METHOD OF MAKING THEREOF 有权
公开(公告)号：US20210082955A1
公开(公告)日：2021-03-18
申请号：US16568668
申请日：2019-09-12
申请人： SANDISK TECHNOLOGIES LLC
发明人： Adarsh RAJASHEKHAR , Raghuveer S. MAKALA , Rahul SHARANGPANI , Seung-Yeul YANG , Fei ZHOU
IPC分类号： H01L27/11597 , H01L27/11587 , H01L27/1159
摘要： A three-dimensional ferroelectric memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, where each of the electrically conductive layers contains a transition metal element-containing conductive liner and a conductive fill material portion, a vertical semiconductor channel extending vertically through the alternating stack, a vertical stack of tubular transition metal element-containing conductive spacers laterally surrounding the vertical semiconductor channel and located at levels of the electrically conductive layers, and a ferroelectric material layer located between the vertical stack of tubular transition metal element-containing conductive spacers and the transition metal element-containing conductive liner.

80. 发明申请

US20210074725A1 VERTICAL-CHANNEL FERROELECTRIC FLASH MEMORY 有权
公开(公告)号：US20210074725A1
公开(公告)日：2021-03-11
申请号：US16749806
申请日：2020-01-22
申请人： MACRONIX INTERNATIONAL CO., LTD.
发明人： Hang-Ting LUE
IPC分类号： H01L27/11597 , H01L23/528 , H01L29/51 , H01L29/78 , H01L27/11592 , G11C11/22
摘要： A device based on 2T vertical ferroelectric memory cells includes a plurality of select gate lines in a first layer, and a plurality of word lines in a second layer, with a plurality of vertical channel structures disposed operably with the select gate lines and word lines. A vertical channel structure of a memory cell in the plurality is disposed orthogonally relative to a corresponding select gate line and a corresponding word line, and forms a channel for the vertical select transistor and the vertical ferroelectric memory transistor. Ferroelectric material is disposed at cross-points between the vertical channel structure and the corresponding word line. A gate dielectric material is disposed at cross-points between the vertical channel structure and the corresponding select gate line. A NOR architecture memory uses the 2T vertical ferroelectric memory cells.

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