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71. 发明授权

US10963624B2 Web UI automation maintenance tool 有权
公开(公告)号：US10963624B2
公开(公告)日：2021-03-30
申请号：US15969044
申请日：2018-05-02
申请人： Citrix Systems, Inc.
发明人： Arnav Akhoury , Sreekanth Challa
IPC分类号： G06F9/455 , G06F40/14 , G06F8/65 , G06F16/958 , G06F11/26
摘要： A web UI automation maintenance tool includes a memory and a processor. The memory stores UI automation scripts for an initial web page that includes elements to be displayed for the web page, with each element having an element identifier. The processor determines web page specifics for the initial web page, including the attributes for each of the elements. After the initial web page has been updated, the processor determines the web page specifics for the updated web page. The processor compares, for each element, attributes from the initial web page to the updated web page, and identifies a new element identifier for each element that changed from the initial web page to the updated web page. The UI automation script in the memory is updated with the new element identifiers for each element whose element identifier has changed.

72. 发明授权

US10962595B1 Efficient realization of coverage collection in emulation 有权
公开(公告)号：US10962595B1
公开(公告)日：2021-03-30
申请号：US16192660
申请日：2018-11-15
申请人： Synopsys, Inc.
发明人： Leonid Alexander Broukhis , Boris Gommershtadt , Florent Duru , Gabriel Gouvine , Dmitry Korchemny
IPC分类号： G01R31/3185 , G06F11/26 , G06F9/30 , G06F11/267 , G06F30/331 , G01R31/327
摘要： Coverage event counters for hardware verification emulations are implemented as linear feedback shift register-based counters generating encoded counter values indicative of a detected number of coverage events. To decode those counter values, a counter algorithm utilized to generate the encoded counter value may continue to be iterated after counting is complete until reaching a defined pattern, while counting the number of iterations (K) necessary to reach the defined pattern. The resulting counter value having the defined pattern is correlated with a mapping table to identify a numerical value, and an ordinal counter value indicative of the number of coverage events is determined based on the identified numerical value, less K.

73. 发明申请

US20210088585A1 AT-SPEED TEST ACCESS PORT OPERATIONS 有权
公开(公告)号：US20210088585A1
公开(公告)日：2021-03-25
申请号：US17117532
申请日：2020-12-10
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Lee D. Whetsel
IPC分类号： G01R31/3177 , G01R31/3185 , G06F11/26 , G01R31/317 , H01L27/32 , H01L51/52 , H01L51/56
摘要： This disclosure describes different ways to improve the operation of a device's 1149.1 TAP to where the TAP can perform at-speed Update & Capture, Shift & Capture and Back to Back Capture & Shift operations. In a first embodiment of the disclosure the at-speed operations are achieved by time division multiplexing CMD signals onto the TMS input to the TAP. The CMD signals are input to a CMD circuit that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit. In a second embodiment of the disclosure the at-speed operations are achieved by detecting the TAP's Exit1DR state as a CMD signal that is input to the CMD circuit that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit. In a third embodiment of the disclosure the at-speed operations are achieved by detecting the TAP's Exit1DR and PauseDR states and in response producing Capture and Update signals that are input to a Programmable Switch that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit. In a fourth embodiment of the disclosure the at-speed operations are achieved by detecting the TAP's Exit1DR and PauseDR states and inputting these states to a Dual Port Router to control the at-speed operations of a circuit. Each of the embodiments may be augmented to include externally accessible Update and Capture input signals that can be selected to allow a tester to directly control the at-speed operations of a circuit. The improvements of the disclosure are achieved without requiring any additional IC pins beyond the 4 required TAP pins, except for examples showing use of additional data input pins (TDI or WPI signals), additional data output pins (TDO or WPO signals) or examples showing use of additional control input pins (Capture and Update signals). Devices including the TAP improvements can be operated compliantly in a daisy-chain arrangement with devices that don't include the TAP improvements.

74. 发明授权

US10929582B2 Circuit validation for circuits comprising multiple possible variants for individual components 有权
公开(公告)号：US10929582B2
公开(公告)日：2021-02-23
申请号：US16089408
申请日：2017-03-31
申请人： Mentor Graphics Corporation
发明人： Michael Alam
IPC分类号： G06F30/33 , G06F30/367 , G06F30/347 , G06F30/333 , G06F11/26
摘要： Circuits may be designed using computer aided design tools and may comprise a plurality of different possible variants of individual components. These multi-variant component circuits may be validated to identify potential problems by generating an aggregate parametric model for the multi-variant components and then using the aggregate parametric model in applying tests to different connection networks of the circuit definition.

75. 发明授权

US10929261B1 Device diagnosis 有权
公开(公告)号：US10929261B1
公开(公告)日：2021-02-23
申请号：US16017736
申请日：2018-06-25
申请人： Amazon Technologies, Inc.
发明人： Alex Levin , Ziv Harel , Evgeny Khanin , David Ben-Dror , Georgy Machulsky , Daniel Elkaslassy , Sergei Shtern
IPC分类号： G06F11/26 , G06Q30/00 , H04L29/08
摘要： A technology is described for a device diagnosis station. The device diagnosis station may be configured to identify an electronic device physically connected to the device diagnosis station, evaluate an operational state of the electronic device by executing testing instructions configured to test the functionality of the electronic device and collect operational state information for the electronic device. The device diagnosis station may be configured to determine the operational state of the electronic device and execute recovery instructions to restore the electronic device to an improved state when a recoverable error is detected. The device diagnosis station may be configured to initiate a device return procedure for the electronic device when a non-recoverable error state is detected.

76. 发明授权

US10914785B2 Testing method and testing system 有权
公开(公告)号：US10914785B2
公开(公告)日：2021-02-09
申请号：US16524304
申请日：2019-07-29
申请人： Realtek Semiconductor Corporation
发明人： Chihtung Chen , Hsing-Han Tseng , Yi-Te Yeh , Yung-Jen Chen , Te-Ming Kuo
IPC分类号： G01R31/3177 , G01R31/3185 , G01R31/3181 , G06F11/26
摘要： The present disclosure provides a testing method and a testing system. The testing method is performed by at least one processor and includes the following operations: converting a circuit data of a scan test to a program, in which the program is configured to observe an untested part of a circuitry that is unable to be tested in the scan test; generating a waveform data associated with the untested part; generating a look-up table according to the program and a netlist file, in which the netlist file indicates the circuitry; and testing the untested part of the circuitry according to the waveform data and the look-up table.

77. 发明授权

US10853214B2 Application processor, automotive electronic processor, and computing device including application processor 有权
公开(公告)号：US10853214B2
公开(公告)日：2020-12-01
申请号：US16058713
申请日：2018-08-08
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Jae-Heon Lee
IPC分类号： G06F11/00 , G06F11/26 , G06F11/273 , G06F11/07 , G06F11/22 , G06F1/3203
摘要： An application processor includes a central processing unit, a root complex that communicates with at least one external device under control of the central processing unit and generates a state change interrupt when an operation state changes, and an interrupt aggregation and debug unit that performs debugging on at least one component associated with the state change interrupt depending on the state change interrupt.

78. 发明申请

US20200371886A1 MULTI-LANE SOLUTIONS FOR ADDRESSING VECTOR ELEMENTS USING VECTOR INDEX REGISTERS 审中-公开
公开(公告)号：US20200371886A1
公开(公告)日：2020-11-26
申请号：US16417526
申请日：2019-05-20
申请人： Micron Technology, Inc.
发明人： Steven Jeffrey Wallach
IPC分类号： G06F11/26 , G06F11/22 , G06F9/30
摘要： Disclosed herein are vector index registers for storing or loading indexes of true and/or false results of conditional operations using multiple lane processing in vector processors. Each of the vector index registers store multiple addresses for accessing multiple positions in operand vectors in various types of operations that can leverage multi-lane processing.

79. 发明申请

US20200349042A1 TECHNIQUES AND SYSTEM FOR OPTIMIZATION DRIVEN BY DYNAMIC RESILIENCE 审中-公开
公开(公告)号：US20200349042A1
公开(公告)日：2020-11-05
申请号：US16931618
申请日：2020-07-17
申请人： Capital One Services, LLC
发明人： Bhavik GUDKA , Eric BARNUM
IPC分类号： G06F11/26 , G06F11/34 , H04L12/24 , G06F11/07 , H04L12/26
摘要： Disclosed are hardware and techniques for testing computer processes in a network system by simulating computer process faults and identifying risk associated with correcting the simulated fault and identifying computer processes that may depend on the corrected computer process. The interdependent computer processes in a network may be determined by evaluating a risk matrix having a risk score and non-functional requirement score. An analysis of the risk score and non-functional requirement score accounts for interdependencies between computer processes and identified corrective actions that may be used to determine an optimal network environment. The optimal network environment may be updated dynamically based on changing computer process interdependencies and the determined risk and robustness scores.

80. 发明授权

US10824528B2 Techniques and system for optimization driven by dynamic resilience 有权
公开(公告)号：US10824528B2
公开(公告)日：2020-11-03
申请号：US16202048
申请日：2018-11-27
申请人： Capital One Services, LLC
发明人： Bhavik Gudka , Eric Barnum
IPC分类号： G06F11/00 , G06F11/26 , G06F11/07 , G06F11/34 , H04L12/26 , H04L12/24
摘要： Disclosed are hardware and techniques for testing computer processes in a network system by simulating computer process faults and identifying risk associated with correcting the simulated fault and identifying computer processes that may depend on the corrected computer process. The interdependent computer processes in a network may be determined by evaluating a risk matrix having a risk score and non-functional requirement score. An analysis of the risk score and non-functional requirement score accounts for interdependencies between computer processes and identified corrective actions that may be used to determine an optimal network environment. The optimal network environment may be updated dynamically based on changing computer process interdependencies and the determined risk and robustness scores.

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