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71. 发明申请

US20040167752A1 Method of assisting wiring design of wiring structure, its apparatus and its program 审中-公开
标题翻译：协助布线结构布线设计及其设备及方案
公开(公告)号：US20040167752A1
公开(公告)日：2004-08-26
申请号：US10669644
申请日：2003-09-25
申请人： YAZAKI CORPORATION
发明人： Masayoshi Sawai
IPC分类号： G06F017/50
CPC分类号： B60R16/0207 , G06F17/509 , G06F2217/36
摘要： A method of assisting a wiring design of a wiring structure includes the steps of: regarding the wiring structure constituted by a plurality of pieces of line streak members as an elastic body which has a circular section and in which a plurality of beam elements a linearity of which is maintained are coupled with each other; applying information concerning a shape characteristic, a material characteristic and a constraining condition of the wiring structure as a predetermined condition to a finite element method; calculating a predicted shape of the displaced wiring structure such that the predetermined condition is satisfied; further calculating a characteristic value with respect to vibration for the calculated predicted shape; and outputting the calculated predicted shape and the calculated characteristic value.
摘要翻译：一种辅助布线结构的布线设计的方法包括以下步骤：关于由具有圆形截面的弹性体的多条线条构件构成的布线结构，其中多个梁单元的线性被保持的相互耦合; 将关于作为预定条件的布线结构的形状特性，材料特性和约束条件的信息应用于有限元方法; 计算所述位移布线结构的预测形状，使得满足所述预定条件; 进一步计算相对于计算出的预测形状的振动的特征值; 并输出计算出的预测形状和计算出的特征值。

72. 发明申请

US20040163059A1 Method and system for entropy driven verification 有权
标题翻译：用于熵驱动验证的方法和系统
公开(公告)号：US20040163059A1
公开(公告)日：2004-08-19
申请号：US10370165
申请日：2003-02-19
发明人： Saravanan Subbarayan
IPC分类号： G06F017/50 , G06F009/45
CPC分类号： G06F17/5009 , G06F17/504 , G06F2217/10
摘要： A microelectronic device design verification system and method estimates the entropy of stimuli communicated over an interface to verify a microelectronic device design and feeds back the estimated entropy to alter the generation of stimuli to improve the design state space verified by additional stimuli applied to the microelectronic device design. For instance, predetermined factors used for random or directed generation of stimuli are altered based on the estimated entropy of stimuli communicated over an interface to a microelectronic device design software model or hardware integrated circuit implementation. The predetermined factors are adjusted so that subsequent stimuli has a desired impact on the estimated entropy, such as an increase in entropy that indicates a more complete microelectronic device design verification.
摘要翻译：微电子器件设计验证系统和方法估计在界面上传送的刺激的熵以验证微电子器件设计并反馈估计的熵以改变刺激的产生，以改善通过施加到微电子器件的附加刺激来验证的设计状态空间设计。例如，用于随机或定向产生刺激的预定因子基于通过界面传递到微电子器件设计软件模型或硬件集成电路实现的刺激的估计熵来改变。调整预定因子，使得随后的刺激对估计的熵具有期望的影响，例如表示更完整的微电子器件设计验证的熵增加。

73. 发明申请

US20040163053A1 Efficient pipelining of synthesized synchronous circuits 失效
标题翻译：合成同步电路的高效流水线
公开(公告)号：US20040163053A1
公开(公告)日：2004-08-19
申请号：US10775945
申请日：2004-02-10
申请人： Hewlett-Packard Company
发明人： Gregory S. Snider
IPC分类号： G06F017/50
CPC分类号： G06F17/5045
摘要： Method and apparatus for generating a pipelined synchronized circuit representation of a program loop. A dependence graph is generated from the program loop. The dependence graph represents operations and registers and connections therebetween. A minimum clock period and initiation interval are determined from the dependence graph. Until a scheduled graph is successfully generated, repeated attempts are made to generate a scheduled graph from operations and registers of the dependence graph using the minimum clock period and the initiation interval. With each failed attempt to generate a scheduled graph, the minimum clock period is increased prior to the next attempt to generate a scheduled graph.
摘要翻译：用于生成程序循环的流水线同步电路表示的方法和装置。从程序循环生成依赖图。依赖图表示其间的操作和寄存器和连接。从依赖图确定最小时钟周期和起始间隔。直到成功生成计划图，进行重复尝试，以使用最小时钟周期和起始间隔从依赖图的操作和寄存器生成计划图。在每次失败的尝试生成预定图表时，在下一次尝试生成调度图之前，最小时钟周期都会增加。

74. 发明申请

US20040162717A1 System and method for efficiently tracing simulation data in hardware acceleration simulation systems 有权
标题翻译：在硬件加速仿真系统中高效跟踪仿真数据的系统和方法
公开(公告)号：US20040162717A1
公开(公告)日：2004-08-19
申请号：US10366859
申请日：2003-02-14
发明人： Nasser Nouri , Ping-Chih Wu , Mohamed Soufi , David S. Allison
IPC分类号： G06F017/50
CPC分类号： G06F17/5022
摘要： A system for tracing signals for a cycle-based simulation includes a traced signal and a system resources availability information of the cycle-based simulation, a runtime compiler configured to use the system resources availability information to assign a system resource to trace the traced signal, a logic design used with the system resources availability information to generate a simulation image, a first value of the traced signal generated by execution of a simulation image, and a traced signal buffer configured to store the first value and upload the first value.
摘要翻译：用于跟踪用于基于周期的模拟信号的系统包括跟踪信号和基于周期的模拟的系统资源可用性信息，运行时编译器被配置为使用系统资源可用性信息来分配系统资源来跟踪跟踪的信号，与系统资源可用性信息一起使用以生成模拟图像的逻辑设计，通过执行模拟图像生成的跟踪信号的第一值，以及被配置为存储第一值并上传第一值的跟踪信号缓冲器。

75. 发明申请

US20040162716A1 Method and system for modeling logical circuit blocks including transistor gate capacitance loading effects 失效
标题翻译：对逻辑电路块进行建模的方法和系统，包括晶体管栅极电容负载效应
公开(公告)号：US20040162716A1
公开(公告)日：2004-08-19
申请号：US10366439
申请日：2003-02-13
申请人： International Business Machines Corporation
发明人： Barry Lee Dorfman , Thomas Edward Rosser , Jeffrey Paul Soreff
IPC分类号： G06F017/50
CPC分类号： G06F17/5036
摘要： A method and system for modeling logical circuit blocks including transistor gate capacitance loading effects provides improved simulation of logical circuit block transition times and delay times. The non-linear behavior of transistor gates of other logical circuit block inputs that are connected to the logical circuit block output is taken into account by a transition time function and a delay time function that are each separately dependent on static capacitance and transistor gate capacitance and can be used to determine logical circuit block timing and output performance. A separate N-channel and P-channel gate capacitance may also be used as inputs to the transition time and delay time functions to provide further improvement, or a ratio of N-channel to P-channel capacitances may alternatively be used as input to the transition time and delay time functions.
摘要翻译：用于对包括晶体管栅极电容负载效应的逻辑电路块进行建模的方法和系统提供了对逻辑电路块转换时间和延迟时间的改进的仿真。通过转换时间函数和延迟时间函数考虑连接到逻辑电路块输出的其他逻辑电路块输入的晶体管栅极的非线性行为，其分别取决于静态电容和晶体管栅极电容，可用于确定逻辑电路块的时序和输出性能。单独的N沟道和P沟道栅极电容也可以用作转换时间和延迟时间函数的输入以提供进一步的改进，或者N沟道与P沟道电容的比率可以替代地用作转换时间和延迟时间功能。

76. 发明申请

US20040162713A1 Modeling pin depths associated with coaxial standards 审中-公开
标题翻译：建模与同轴标准相关的销深度
公开(公告)号：US20040162713A1
公开(公告)日：2004-08-19
申请号：US10365882
申请日：2003-02-13
发明人： David VerNon Blackham , Kenneth H. Wong , James R. Myers
IPC分类号： G06F017/50
CPC分类号： G06F17/5036
摘要： A modeling method modifies a nominal model for a coaxial standard to provide an enhanced model for the coaxial standard. The nominal model is a nominal reflection coefficient that is phase rotated and impedance transformed to provide an enhanced reflection coefficient that represents the enhanced model. Alternatively, a transmission matrix for the coaxial standard is established and converted to an S-parameter matrix. The enhanced model is then extracted from the nominal model and the S-parameter matrix using network analysis techniques.
摘要翻译：建模方法修改同轴标准的标称模型，以提供同轴标准的增强型号。标称模型是相位旋转和阻抗变换的标称反射系数，以提供表示增强模型的增强反射系数。或者，建立用于同轴标准的传输矩阵并将其转换为S参数矩阵。然后使用网络分析技术从标称模型和S参数矩阵中提取增强模型。

77. 发明申请

US20040158803A1 Integrated circuit, integrated circuit design method and hardware description generation method to generate hardware behavior description of integrated circuit 失效
公开(公告)号：US20040158803A1
公开(公告)日：2004-08-12
申请号：US10770479
申请日：2004-02-04
申请人： Hitachi, Ltd.
发明人： Masaki Ito
IPC分类号： G06F017/50
CPC分类号： G06F17/5045
摘要： A functional block for verifying correct interface operation of any functional block is generated from interface description and installed on a LSI chip. To accomplish this, from the interface description, hardware description of a synthesizable interface checker is generated. Means for selecting interface functions to be checked is provided, thereby making it possible to reduce the overhead of circuits to be installed on the LSI.

78. 发明申请

US20040153981A1 Generation of clock gating function for synchronous circuit 有权
标题翻译：同步电路生成时钟选通功能
公开(公告)号：US20040153981A1
公开(公告)日：2004-08-05
申请号：US10761156
申请日：2004-01-20
发明人： Stephen Paul Wilcox , Paul Alexander Cunningham
IPC分类号： G06F017/50
CPC分类号： G06F17/5045
摘要： There is disclosed a method, and corresponding apparatus, for determining a clock gating function for a set of clocked state-holding elements, comprising the steps of: for each element, determining the conditions under which the element will hold its current value based only on those inputs which are common to all elements; and combining the conditions to form a gating function.
摘要翻译：公开了一种用于确定一组时钟状态保持元件的时钟门控功能的方法和相应的装置，包括以下步骤：对于每个元件，确定元件将仅基于所有要素共同的投入; 并结合条件形成门控功能。

79. 发明申请

US20040153930A1 Method of generating test pattern for integrated circuit 失效
标题翻译：生成集成电路测试图案的方法
公开(公告)号：US20040153930A1
公开(公告)日：2004-08-05
申请号：US10736934
申请日：2003-12-16
发明人： Hisashi Yamauchi
IPC分类号： G06F017/50 , G06F011/00 , G01R031/28
CPC分类号： G01R31/318547 , G01R31/318321 , G01R31/318342
摘要： A method for preventing the scale of a circuit from being extended and for preventing noise from being generated by a simultaneous value change in output buffers includes: the first process of checking the number of output buffers 15A through 15D whose output values change when boundary scan cells 13E through 13H output input patterns; the second process of checking the noise value generated by the change in the output values when all output values from the output buffers checked in the first process change; the third process of selecting the output buffer from the buffers checked in the first process such that the noise value checked in the second process can be within the noise allowable value; and the fourth process of outputting as a test pattern a pattern obtained by amending the input pattern such that the output value of the output buffer selected in the third process can change.
摘要翻译：一种防止电路规模扩展并防止由输出缓冲器的同时变化产生噪声的方法包括：检查输出缓冲器15A至15D的数量的第一过程，其输出值在边界扫描单元 13E至13H输出输出模式; 当在第一过程中检查的所有输出缓冲器的所有输出值改变时，检查由输出值变化产生的噪声值的第二过程; 从在第一处理中检查的缓冲器中选择输出缓冲器的第三过程，使得在第二处理中检查的噪声值可以在噪声允许值内; 以及作为测试图案输出通过修改输入图案而获得的图案的第四过程，使得在第三处理中选择的输出缓冲器的输出值可以改变。

80. 发明申请

US20040153303A1 Efficient process for time dependent network model in an energy market simulation system 审中-公开
标题翻译：能源市场模拟系统中时间依赖网络模型的有效过程
公开(公告)号：US20040153303A1
公开(公告)日：2004-08-05
申请号：US10744386
申请日：2003-12-23
发明人： Le Tang , Xiaoming Feng
IPC分类号： G06F017/50
CPC分类号： G06F17/5022
摘要： A method and system for efficiently simulating an electric power transmission network is disclosed. In the method, a parameterized value is assigned to an element in the network that is present during any time interval of a simulation test period. If an element in the network has changed from a preceding time interval, the network of the preceding time interval is updated by changing the parameterized value for the changed element, and the updated network is simulated. If any element in the network has not changed from the network of the preceding time interval, the network is simulated based on the network of the preceding time interval.
摘要翻译：公开了一种有效地模拟电力传输网络的方法和系统。在该方法中，将参数化值分配给网络中在模拟测试周期的任何时间间隔期间存在的元素。如果网络中的元素从前一时间间隔发生变化，则通过更改已更改元素的参数值来更新前一时间间隔的网络，并更新已更新的网络。如果网络中的任何元素没有从前一时间间隔的网络发生变化，则基于前一时间间隔的网络模拟网络。

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